A. Sharma, Jason Martin, N. Anand, M. Cukier, W. Sanders
{"title":"Ferret: a host vulnerability checking tool","authors":"A. Sharma, Jason Martin, N. Anand, M. Cukier, W. Sanders","doi":"10.1109/PRDC.2004.1276595","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276595","url":null,"abstract":"Evaluation of computing system security requires knowledge of the vulnerabilities present in the system and of potential attacks against the system. Vulnerabilities can be classified based on their location as application vulnerabilities, network vulnerabilities, or host vulnerabilities. We describe Ferret, a new software tool for checking host vulnerabilities. Ferret helps system administrators by quickly finding vulnerabilities that are present on a host. It is designed and implemented in a modular way: a different plug-in module is used for each vulnerability checked, and each possible output format is specified by a plug-in module. As a result, Ferret is extensible, and can easily be kept up-to-date through addition of checks for new vulnerabilities as they are discovered; the modular approach also makes it easy to provide specific configurations of Ferret tailored to specific operating systems or use environments. Ferret is a freely available open-source software implemented in Perl.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128052717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault-tolerant message switching based on wormhole switching and backtracking","authors":"Manabu Sueishi, M. Kitakami, Hideo Ito","doi":"10.1109/PRDC.2004.1276569","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276569","url":null,"abstract":"Parallel computers are now popularly applied to applications where many calculations are required. In a NO Remote memory Access model (NORA) parallel computer, many processors are connected by communication links and calculation results are obtained by communications among processors. The message switching method, which controls message transmission in the parallel computer, is one of the most important parameters to improve the performance of the parallel computer. Since parallel computers include many processors, its failure rate is very high and many fault-tolerant switching methods have been proposed. The existing methods have problems, however, such as low communication throughput, low fault-tolerant capability, and large hardware overhead. We propose fault-tolerant switching by improving wormhole switching. The proposed method inserts dummy flits, having no information, after the header flit, the first flit of the packet. By overwriting the header flit to the dummy flit, backtracking is implemented without hardware overhead. Computer simulation says that in a 16 by 16 2D torus, for example, the throughput of the proposed method is almost equal to that of existing methods which require large hardware overhead if the number of the faulty nodes is less then 40.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130511101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Arai, Tabito Suzuki, Mamoru Ohara, S. Fukumoto, K. Iwasaki, H. Youn
{"title":"Analysis of read and write availability for generalized hybrid data replication protocol","authors":"M. Arai, Tabito Suzuki, Mamoru Ohara, S. Fukumoto, K. Iwasaki, H. Youn","doi":"10.1109/PRDC.2004.1276565","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276565","url":null,"abstract":"Replicating data is a promising way of improving the dependability of large distributed systems. The hybrid data replication protocol combines concepts of the tree quorum protocol and grid protocol. We present an analytical evaluation of read/write availability for the generalized hybrid data replication protocol, which extends the arrangement of nodes into a more general form to improve write availability. The average number of nodes accessed for read/write operations is also analyzed under the assumption that nodes might fail. Equations are derived based on node availability p, and numerical examples are shown. We use computer simulations to estimate the throughput for read/write operations.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124149785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Software rejuvenation policies for cluster systems under varying workload","authors":"Wei Xie, Yiguang Hong, Kishor S. Trivedi","doi":"10.1109/PRDC.2004.1276563","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276563","url":null,"abstract":"We analyze two software rejuvenation policies of cluster server systems under varying workload, called fixed rejuvenation and delayed rejuvenation. In order to achieve a higher average throughput, we propose the delayed rejuvenation policy, which postpones the rejuvenation of individual nodes until off-peak hours. Analytic models using the well known paradigm of Markov chains are used. Since the size of the Markov model is nontrivial, automated specification generation, and the solution via stochastic Petri nets is utilized. Deterministic time to trigger rejuvenation is approximated by a 20-stage Erlangian distribution. Based on the numerical solutions of the models, we find that under the given context, although the fixed rejuvenation occasionally yields a higher throughput, the delayed rejuvenation policy seems to outperform fixed rejuvenation policy by up to 11%. We also compare the steady-state system availabilities of these two rejuvenation policies.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129763894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Node-to-node internally disjoint paths problem in bubble-sort graphs","authors":"K. Kaneko, Yasuto Suzuki","doi":"10.1109/PRDC.2004.1276568","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276568","url":null,"abstract":"A bubble-sort graph is a variant of Cayley graphs and it is suitable as a topology for massively parallel systems because of its simple and regular structure. Therefore, we focus on nth bubble-sort graphs and propose an algorithm to obtain n-1 disjoint paths between arbitrary two nodes in the complexity of polynomial order of n which is the degree of the graph plus one. We estimate the time complexity of the algorithm and the sum of path lengths after proving the correctness of the algorithm. Moreover, we report the results of computer experiment to evaluate average performance of the algorithm.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130413808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient built-in self-test techniques for memory-based FFT processors","authors":"Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin","doi":"10.1109/PRDC.2004.1276582","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276582","url":null,"abstract":"Efficient built-in self-test techniques for memory-based FFT processors are proposed. The memory-based architecture is suitable for high computation point applications such as ADSL and OFDM systems. The FFT processor is first divided into the memory part and the logic part which can be tested under the supervision of the same BIST controller. The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part. The adopted memory test algorithm can be programmed by the users which covers different types of memory faults. For the logic part, the single cell fault model is assumed. Our BIST architecture tests both parts simultaneously such that the test time can be reduced greatly. The hardware overhead of our approach is also very low since novel design-for-testability techniques are applied for the logic part which mainly consists of multipliers. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture is only 4.06%. The fault coverage of the memory part depends on the March algorithm adopted. For the logic part, we can achieve 100% cell fault coverage with only 16 test patterns.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134223030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bondavalli, E. Giudici, S. Porcarelli, Salvatore Sabina, F. Zanini
{"title":"A freshness detection mechanism for railway applications","authors":"A. Bondavalli, E. Giudici, S. Porcarelli, Salvatore Sabina, F. Zanini","doi":"10.1109/PRDC.2004.1276579","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276579","url":null,"abstract":"Railway control systems are based on on-board and trackside subsystems for signaling purposes. Several factors demand for new design and implementation solutions for such railway control systems. These factors are related to the design of interoperable railway networks in Europe, the introduction of new technologies and equipment, and the competition in the market of railway products. The safety of such new design and implementation solutions should still be proved in accordance with the CENELEC recommendations. SFDA, safe message freshness detection algorithm among trackside subsystems, is deeply described. SFDA is included in a new message passing safety protocol stack and it allows the detection of \"old\" messages and the meeting of real time and safety requirements of trackside railway systems. It is demonstrated that the SFDA can detect all the old messages. Moreover a preliminary analysis of its availability characteristics to check whether it is suitable for railways systems is performed through simulation.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134574461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Periodic partial validation: cost-effective source code validation process in cross-platform software development environment","authors":"Sheng Li, Jun Xu, Lijun Deng","doi":"10.1109/PRDC.2004.1276597","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276597","url":null,"abstract":"Enterprise software development typically involves cooperation among multiple entities. In a cross-platform software development environment, developers can categorize the source code of products into platform specific and platform generic components, so that common features can be deployed seamlessly across platforms. As the complexity of component and source code inter-dependency increases, build breakages occur more frequently, and the lack of an efficient detection mechanism often results in slow response with higher costs. We present a successful cost-effective method to automatically detect and identify such breakages. We deployed a centralized code validation and policing tool, and the results prove its effectiveness as an important quality assurance component in the software development process.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132869840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability evaluation of dependable distributed computing systems based on recursive merge and BDD","authors":"Yung-Ruei Chang, Hung-Yau Lin, S. Kuo","doi":"10.1109/PRDC.2004.1276570","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276570","url":null,"abstract":"System reliability evaluation, sensitivity analysis, importance measures, failure frequency analysis and optimal design have become important issues for distributed dependable computing. Finding all the minimal file spanning trees (MFST) and avoiding repeatedly computing the redundant MFSTs is the key technique for evaluating the reliability of a distributed computing system (DCS) in previous works. However, identifying all the disjoint MFSTs is difficult and very time consuming for large-scale networks. Although existing algorithms have been demonstrated that they work fine on medium-scale networks, they have two inherent drawbacks. First, they do not support efficient manipulation of Boolean algebra. The sum-of-disjoint-products method used by them is inefficient in dealing with large Boolean functions. Second, the tree-based partitioning algorithm does not merge isomorphic subproblems and therefore, redundant computations cannot be avoided. We propose a new efficient algorithm for the reliability evaluation of a DCS based on recursive merge and binary decision diagram (BDD). Using the BDD substitution technique, we can easily apply our algorithm to a network with imperfect nodes. The experimental results show a significant improvement on the execution time compared to previous works.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133773761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nonsystematic M-ary asymmetric error correcting codes designed by multilevel coding method","authors":"H. Kaneko, Mariko Numakami, E. Fujiwara","doi":"10.1109/PRDC.2004.1276572","DOIUrl":"https://doi.org/10.1109/PRDC.2004.1276572","url":null,"abstract":"Nonbinary M-ary words processed by data entry systems often suffer from asymmetric errors. In character recognition systems, for example, two symbols a/sub i/ and a/sub j/ with similar shapes have a high probability of being mistaken for one another. Among the many types of data processed by data entry systems, M-ary words selected from a specified codebook, such as postal codes and product numbers, should be strongly protected from asymmetric errors because these words are often used for indexing a database. We propose a new class of nonsystematic M-ary asymmetric error correcting codes which can be utilized to generate these codebooks. In order to effectively correct asymmetric errors, the new class of codes is designed based on a multilevel coding method and a set partitioning algorithm. Evaluation shows that the proposed codes have a low decoded symbol error rate.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124877009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}