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2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems最新文献

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Accelerated Functional Testing of Digital Microfluidic Biochips 数字微流体生物芯片的加速功能测试
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-11-24 DOI: 10.1109/ATS.2008.48
D. Mitra, S. Ghoshal, H. Rahaman, B. Bhattacharya, D. Majumder, K. Chakrabarty
{"title":"Accelerated Functional Testing of Digital Microfluidic Biochips","authors":"D. Mitra, S. Ghoshal, H. Rahaman, B. Bhattacharya, D. Majumder, K. Chakrabarty","doi":"10.1109/ATS.2008.48","DOIUrl":"https://doi.org/10.1109/ATS.2008.48","url":null,"abstract":"Structural testing of digital microfluidic biochips targets the detection of physical defects, but it does not guarantee robust execution of target bioassays or the integrity of assay outcomes. Functional testing is needed to detect fluidic malfunctions. Such tests ensure, whether or not, the elementary fluidic operations, such as droplet transportation, mixing, incubation, and splitting are reliably executed on the microfluidic array. Routing test and mixing/splitting test are two most important functional test procedures. We present two procedures for optimal bidirectional routing test and accelerated mixing/splitting test. Compared to previous methods, these procedures need significantly fewer droplet manipulation steps and reduced execution time. The proposed method of functional testing in an N x N microfluidic array requires only a constant number of mixing/splitting steps. Further, the test outcome is free from boundary errors related to droplet size that may arise during mixing/splitting test.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133258334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (Low) 具有逻辑擦洗的可重构组件的案例:定期卫生保持逻辑适合(低)
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.17
A. DeHon
{"title":"The Case for Reconfigurable Components with Logic Scrubbing: Regular Hygiene Keeps Logic FIT (Low)","authors":"A. DeHon","doi":"10.1109/NDCS.2008.17","DOIUrl":"https://doi.org/10.1109/NDCS.2008.17","url":null,"abstract":"As we approach atomic-scale logic, we must accommodate an increased rate of manufacturing defects, transient upsets, and in-field persistent failures. High defect rates demand reconfiguration to avoid defective components, and transient upsets demand online error detection to catch failures. Combining these techniques we can detect in-field persistent failures when they occur and reconfigure around them. However, since failures may be logically masked for long periods of time, persistent failures may accumulate silently; this integration of errors over time means the effective failure rate for persistent errors can exceed transient upset rates. As a result, logic scrubbing is necessary to prevent the silent accumulation of an undetectable number of persistent errors. We provide simple analysis to illustrate quantitatively how this phenomena can be a concern.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122264391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Programmable Comparators Based Array for Regular QCA Implementation 基于可编程比较器阵列的常规QCA实现
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.14
V. Ostrovsky, O. Keren, I. Levin
{"title":"Programmable Comparators Based Array for Regular QCA Implementation","authors":"V. Ostrovsky, O. Keren, I. Levin","doi":"10.1109/NDCS.2008.14","DOIUrl":"https://doi.org/10.1109/NDCS.2008.14","url":null,"abstract":"The paper presents a novel universal quantum cellular automata (QCA) gate called boundary comparator. This gate implements a Boolean function in its boundary form, which is a superposition of elementary boundary functions i.e. a threshold function having weights equal to integer powers of 2. The boundary comparators are arranged in a form of array forming homogeneous programmable structure. The paper proposes a method of synthesis of Boolean functions on the base of boundary functions. The method uses autocorrelation values of the initial function for minimization of a number of bounds. The structures of the boundary comparator as well as the structure of the comparator-based array are presented. Benchmark results allow evaluating efficiency of the proposed structure in comparison with known QCA solutions.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132897987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Yield Estimation of Molecular QCA Memory Structures with Geometric Analysis 基于几何分析的分子QCA记忆结构产率估计
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.24
T. J. Dysart, D.J. Lohmer, P. Kogge
{"title":"Yield Estimation of Molecular QCA Memory Structures with Geometric Analysis","authors":"T. J. Dysart, D.J. Lohmer, P. Kogge","doi":"10.1109/NDCS.2008.24","DOIUrl":"https://doi.org/10.1109/NDCS.2008.24","url":null,"abstract":"Nanoelectronic devices and circuits are likely to contain multiple defects and exhibit faulty behavior, especially as larger circuits are built. In this work, we will present a new method for estimating the yield of memory structures constructed from molecular QCA devices. This method takes patterns of missing cells that were found, via full physical simulation, to cause wire failures and compares them to the geometry of a defective memory-like circuit to determine if the memory-like circuit operates properly. The memory-like structure used here is 'snake' shaped and is a series of straight and bent wire segments. We vary the number of cells between the corners (the aspect ratio), the cell width of the wire segments, the total length of the memory structures, and the percentage of cells that are removed. Our results show that this new method is viable for yield estimation. We also show that computational speedups of several orders of magnitude are achieved by using this method.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New SRAM Cell Design for Low Power and High Reliability Using  32nm Independent Gate FinFET Technology 采用32nm独立栅极FinFET技术设计低功耗、高可靠性的新型SRAM单元
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.16
Young Bok Kim, Yong-Bin Kim, F. Lombardi
{"title":"New SRAM Cell Design for Low Power and High Reliability Using  32nm Independent Gate FinFET Technology","authors":"Young Bok Kim, Yong-Bin Kim, F. Lombardi","doi":"10.1109/NDCS.2008.16","DOIUrl":"https://doi.org/10.1109/NDCS.2008.16","url":null,"abstract":"This paper proposes new methods for SRAM cell design in FinFET technology. One of the most important features of FinFET is that the independent front and back gates can be biased differently to control the current and the device threshold voltage. By controlling the back gate voltage of a FinFET, a SRAM cell can be designed for low power consumption. This paper proposes a new 8T (8 transistors) SRAM structure that reduces dynamic power for the write operation and achieves a wider SNM (static noise margin). Using the new FinFET based 8T SRAM cell, dynamic power consumption is reduced by nearly 48% and the SNM is widened up to 56% compared to the conventional 6T SRAM at the expense of 2% leakage power and 3% write delay increase.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Characterization of the Displacement Tolerance of QCA Interconnects QCA互连位移公差的表征
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.9
F. Karim, K. Waluś
{"title":"Characterization of the Displacement Tolerance of QCA Interconnects","authors":"F. Karim, K. Waluś","doi":"10.1109/NDCS.2008.9","DOIUrl":"https://doi.org/10.1109/NDCS.2008.9","url":null,"abstract":"Quantum-dot cellular automata (QCA) is one of several emerging nanoscale devices that is targeted at scalable molecular electronics. In this paper, the tolerance to cell displacements of a QCA interconnect is analyzed in order to determine limits on allowable displacements, as well as to identify the important failure mechanisms. Numerical simulations using the coherence vector formalism are performed for a short length of QCA interconnect under various conditions. Contrary to previous work, our results indicate that wider interconnects display a higher sensitivity to cell displacements due to the formation of cell clusters, which are more prominent in wider interconnects as a result of the increased number of cells.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122556694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design Tradeoffs for Improved Performance in MQCA-Based Systems 在基于mqca的系统中改进性能的设计权衡
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.23
M. Niemier, A. Dingler, X.S. Hu
{"title":"Design Tradeoffs for Improved Performance in MQCA-Based Systems","authors":"M. Niemier, A. Dingler, X.S. Hu","doi":"10.1109/NDCS.2008.23","DOIUrl":"https://doi.org/10.1109/NDCS.2008.23","url":null,"abstract":"This paper looks at circuits and systems made from nanoscale magnets. We leverage physical level simulation to show how to extend initial experimental work - where wires and gates with nanometer feature sizes have been demonstrated at room temperature - to show how one might make design tradeoffs to improve both the performance and reliability of more complex systems.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122280911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Effects of Channel Orientations, High-? Gate Stacks and Stress on UTB-FETs: A QDD Simulation Study 通道取向的影响，高-?utb - fet的栅极叠加和应力:QDD仿真研究
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.19
L. Silvestri, S. Reggiani, E. Gnani, A. Gnudi, M. Rudan, G. Baccarani
{"title":"Effects of Channel Orientations, High-? Gate Stacks and Stress on UTB-FETs: A QDD Simulation Study","authors":"L. Silvestri, S. Reggiani, E. Gnani, A. Gnudi, M. Rudan, G. Baccarani","doi":"10.1109/NDCS.2008.19","DOIUrl":"https://doi.org/10.1109/NDCS.2008.19","url":null,"abstract":"In this work we propose a unified model for the low-field effective electron mobility in SOI and DG-MOSFETs with ultrathin SiO2/HfO2 gate stacks, different substrate and channel orientations and uniaxial stress conditions.The model accounts for quantum-confinement effects in the MOSFET channel. Next, we apply this mobility model to a 1D quantum drift-diffusion (QDD) transport model in order to investigate the extent to which the low-field mobility impacts the I-V characteristics. Short (Lg = 22 nm) DGFETs,where mobility is affected by quantum-confinement effects, ultrathin SiO2/HfO2 gate stacks and metal gate,have been investigated. Finally, the correlations between the mobility enhancement induced by uniaxial stress in a 22 nm DG-FET, the on-current and transconductance are examined.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129802361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analytical Theory of Graphene Nanoribbon Transistors 石墨烯纳米带晶体管的解析理论
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.22
Pei Zhao, M. Choudhury, K. Mohanram, J. Guo
{"title":"Analytical Theory of Graphene Nanoribbon Transistors","authors":"Pei Zhao, M. Choudhury, K. Mohanram, J. Guo","doi":"10.1109/NDCS.2008.22","DOIUrl":"https://doi.org/10.1109/NDCS.2008.22","url":null,"abstract":"Graphene has emerged as one of the most promising materials to address scaling challenges in the post silicon era. A simple model for graphene nanoribbon field-effect transistors (GNRFETs) is developed for treating the effects of edge bond relaxation, the third nearest neighbor interaction, and edge scattering, all of which are pronounced in GNRFETs, but not in carbon nanotube FETs.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A Graph Model for Tile Sets in DNA Self-Assembly DNA自组装中瓦片集的图模型
2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems Pub Date : 2008-09-29 DOI: 10.1109/NDCS.2008.11
Z. M. Arani, M. Hashempour, F. Lombardi
{"title":"A Graph Model for Tile Sets in DNA Self-Assembly","authors":"Z. M. Arani, M. Hashempour, F. Lombardi","doi":"10.1109/NDCS.2008.11","DOIUrl":"https://doi.org/10.1109/NDCS.2008.11","url":null,"abstract":"This paper deals with a novel graph model to represent tile sets for DNA self-assembly in forward growth under aTAM. This model is based on a tile attachment and captures the features of the so-called corner attachment by considering the binding of the bonds between a tile and the current error-free aggregate. An analysis of this process and its implications on tile sets (such as composition and decomposition) are pursued with respect to the properties of the graph model.","PeriodicalId":378294,"journal":{"name":"2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122845295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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