2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems最新文献

SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores 基于系统c的RTL IP核抽象仿真加速松散模型

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.39

S. Abrar, M. Jenihhin, J. Raik

{"title":"SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores","authors":"S. Abrar, M. Jenihhin, J. Raik","doi":"10.1109/DDECS.2015.39","DOIUrl":"https://doi.org/10.1109/DDECS.2015.39","url":null,"abstract":"The rapid increase of embedded systems design complexity has resulted in emergence of design methodologies at higher levels of abstraction such as Electronic System Level (ESL) and Transaction Level Modeling (TLM) with SystemC language as the main instrument. In practice, system architects and system integrators often have access to a library of legacy Register Transfer Level (RTL) IP (Intellectual Property) cores or obtain new ones from IP design houses. To address architectural exploration, early prototyping and simulation performance, such RTL IP cores are manually recreated at more abstract levels, which implies significant and error-prone effort. The current paper proposes an approach for automated abstraction of the computational part of cycle-accurate RTL IP cores to untimed TLM using a novel concept of SystemC-based Loose Models (SCLM). SCLMs provide for an instrument to neglect design model parts irrelevant for particular manipulation step of the abstraction process, thus simplifying the abstraction flow. As a result, the computational complexity of the abstraction process is reduced, thus increasing the overall scalability. The proposed abstraction flow is demonstrated on a set of benchmark designs and the first experimental results prove feasibility of the proposed approach and also show considerable simulation speed-up.","PeriodicalId":368685,"journal":{"name":"2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115308451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Embedded Test Instrument for On-Chip Phase Noise Evaluation of Analog/IF Signals 片上模拟/中频信号相位噪声评估的嵌入式测试仪

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.11

F. Azaïs, S. David-Grignot, L. Latorre, F. Lefèvre

引用次数: 0

Power-Management Specification in SystemC SystemC电源管理规范

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.16

Dominik Macko, K. Jelemenská, P. Cicák

引用次数: 15

Direct Test Methodology for HDL Verification HDL验证的直接测试方法

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.47

Rados Dabic, Sasa Jednak, Ilija Adzic, Dusko Stanic, Aleksandar Mijatovic, Stanislav Vuckovic

引用次数: 2

NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip 无依赖:一种灵活和可扩展的3D片上网络可靠性技术

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.30

T. Hollstein, Siavoosh Payandeh Azad, Thilo Kogge, Haoyuan Ying, K. Hofmann

引用次数: 4

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs 基于LFSR重播的减压器输出可控性不同的测试压缩

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.28

O. Novák, Jiri Jenícek, M. Rozkovec

引用次数: 1

Activity Profiling and Power Estimation for Embedded Wireless Sensor Node Design 嵌入式无线传感器节点设计的活动分析和功率估计

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.54

G. Panic, Z. Stamenkovic

引用次数: 4

Parameterized Critical Path Selection for Delay Fault Testing 时延故障检测的参数化关键路径选择

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.62

M. Siebert, E. Gramatová

{"title":"Parameterized Critical Path Selection for Delay Fault Testing","authors":"M. Siebert, E. Gramatová","doi":"10.1109/DDECS.2015.62","DOIUrl":"https://doi.org/10.1109/DDECS.2015.62","url":null,"abstract":"Delay faults testing is more and more important due to huge number of gates and lines integrated on a chip. Path delay faults are tested via selected critical paths in a tested digital circuit. The critical paths can be specified e.g. By static timing analysis (STA), statistical static timing analysis (SSTA) and others. Signal delay propagation is also affected by many factors such as power supply noise, multiple input switching, temperature and others during test. The impact of each factor to the path delay faults has been individually solved and published in some papers but their joint effects should be also investigated. A new technique for evaluation of critical paths and a general system for critical paths selection PaCGen have been developed and they are presented in the paper. It is based on STA and influences of multiple factors defined by the new technique for path criticality calculation. Some critical paths can be found as untestable based on structure of the circuit. The proposed system includes more effective DFT technique to change untestable critical paths to testable. Evaluation of the proposed technique has been done over ISCAS-89 benchmark circuits and compared with published results.","PeriodicalId":368685,"journal":{"name":"2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115911053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Intermittent Resistive Faults in Digital CMOS Circuits 数字CMOS电路中的间歇性电阻性故障

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.12

H. Kerkhoff, Hassan Ebrahimi

引用次数: 8

A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm 基于HOE算法的178mhz WXGA 30fps光流处理器设计

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2015-04-22 DOI: 10.1109/DDECS.2015.36

T. Matsumura, Aoi Kurokawa, K. Imamura, Y. Matsuda

引用次数: 1