ACM Symposium on Parallelism in Algorithms and Architectures最新文献

Memory-mapping support for reducer hyperobjects 对reducer超对象的内存映射支持

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312056

I. Lee, A. Shafi, C. Leiserson

{"title":"Memory-mapping support for reducer hyperobjects","authors":"I. Lee, A. Shafi, C. Leiserson","doi":"10.1145/2312005.2312056","DOIUrl":"https://doi.org/10.1145/2312005.2312056","url":null,"abstract":"Reducer hyperobjects (reducers) provide a linguistic abstraction for dynamic multithreading that allows different branches of a parallel program to maintain coordinated local views of the same nonlocal variable. In this paper, we investigate how thread-local memory mapping (TLMM) can be used to improve the performance of reducers. Existing concurrency platforms that support reducer hyperobjects, such as Intel Cilk Plus and Cilk++, take a hypermap approach in which a hash table is used to map reducer objects to their local views. The overhead of the hash table is costly --- roughly 12x overhead compared to a normal L1-cache memory access on an AMD Opteron 8354. We replaced the Intel Cilk Plus runtime system with our own Cilk-M runtime system which uses TLMM to implement a reducer mechanism that supports a reducer lookup using only two memory accesses and a predictable branch, which is roughly a 3x overhead compared to an ordinary L1-cache memory access. An empirical evaluation shows that the Cilk-M memory-mapping approach is close to 4x faster than the Cilk Plus hypermap approach. Furthermore, the memory-mapping approach admits better locality than the hypermap approach during parallel execution, which allows an application using reducers to scale better.","PeriodicalId":367373,"journal":{"name":"ACM Symposium on Parallelism in Algorithms and Architectures","volume":"41 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120923329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Brief announcement: speedups for parallel graph triconnectivity 简短公告:加速并行图三连通性

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312042

J. Edwards, U. Vishkin

引用次数: 9

On the cost of composing shared-memory algorithms 关于编写共享内存算法的代价

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312057

Dan Alistarh, R. Guerraoui, P. Kuznetsov, Giuliano Losa

{"title":"On the cost of composing shared-memory algorithms","authors":"Dan Alistarh, R. Guerraoui, P. Kuznetsov, Giuliano Losa","doi":"10.1145/2312005.2312057","DOIUrl":"https://doi.org/10.1145/2312005.2312057","url":null,"abstract":"Decades of research in distributed computing have led to a variety of perspectives on what it means for a concurrent algorithm to be efficient, depending on model assumptions, progress guarantees, and complexity metrics. It is therefore natural to ask whether one could compose algorithms that perform efficiently under different conditions, so that the composition preserves the performance of the original components when their conditions are met.\u0000 In this paper, we evaluate the cost of composing shared-memory algorithms. First, we formally define the notion of safely composable algorithms and we show that every sequential type has a safely composable implementation, as long as enough state is transferred between modules. Since such generic implementations are inherently expensive, we present a more general light-weight specification that allows the designer to transfer very little state between modules, by taking advantage of the semantics of the implemented object. Using this framework, we implement a composed long-lived test-and-set object, with the property that each of its modules is asymptotically optimal with respect to the progress condition it ensures, while the entire implementation only uses objects with consensus number at most two. Thus, we show that the overhead of composition can be negligible in the case of some important shared-memory abstractions.","PeriodicalId":367373,"journal":{"name":"ACM Symposium on Parallelism in Algorithms and Architectures","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114543321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A parallel buffer tree 并行缓冲树

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312046

Nodari Sitchinava, N. Zeh

引用次数: 11

Brief announcement: subgraph isomorphism on a multithreaded shared memory architecture 简短声明:多线程共享内存架构上的子图同构

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312019

C. Ralph, V. Leung, William C. McLendon

引用次数: 0

A scalable framework for heterogeneous GPU-based clusters 基于gpu的异构集群的可扩展框架

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312025

Fengguang Song, J. Dongarra

{"title":"A scalable framework for heterogeneous GPU-based clusters","authors":"Fengguang Song, J. Dongarra","doi":"10.1145/2312005.2312025","DOIUrl":"https://doi.org/10.1145/2312005.2312025","url":null,"abstract":"GPU-based heterogeneous clusters continue to draw attention from vendors and HPC users due to their high energy efficiency and much improved single-node computational performance, however, there is little parallel software available that can utilize all CPU cores and all GPUs on the heterogeneous system efficiently. On a heterogeneous cluster, the performance of a GPU (or a compute node) increases in a much faster rate than the performance of the PCI-Express connection (or the interconnection network) such that communication eventually becomes the bottleneck of the entire system. To overcome the bottleneck, we developed a multi-level partitioning and distribution method that guarantees a near-optimal communication volume. We have also extended heterogeneous tile algorithms to work on distributed memory GPU clusters. Our main idea is to execute a serial program and generate hybrid-size tasks, and follow a dataflow programming model to fire the tasks on different compute nodes. We then devised a distributed dynamic scheduling runtime system to schedule tasks, and transfer data between hybrid CPU-GPU compute nodes transparently. The runtime system employs a novel distributed task-assignment protocol to solve data dependencies between tasks without coordination between processing units. The runtime system on each node consists of a number of CPU compute threads, a number of GPU compute threads, a task generation thread, an MPI communication thread, and a CUDA communication thread. By overlapping computation and communication through dynamic scheduling, we are able to attain a high performance of 75 TFlops for Cholesky factorization on the heterogeneous Keeneland system using 100 nodes, each with twelve CPU cores and three GPUs. Moreover, our framework is able to attain high performance on distributed-memory clusters without GPUs, and shared-system multiGPUs.","PeriodicalId":367373,"journal":{"name":"ACM Symposium on Parallelism in Algorithms and Architectures","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134557648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

In search of parallel dimensions 寻找平行维度

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312012

Ravi Rajwar

引用次数: 0

Lower bounds for restricted-use objects: extended abstract 限制使用对象的下界:扩展抽象

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312037

J. Aspnes, H. Attiya, K. Censor-Hillel, Danny Hendler

{"title":"Lower bounds for restricted-use objects: extended abstract","authors":"J. Aspnes, H. Attiya, K. Censor-Hillel, Danny Hendler","doi":"10.1145/2312005.2312037","DOIUrl":"https://doi.org/10.1145/2312005.2312037","url":null,"abstract":"Concurrent objects play a key role in the design of applications for multi-core architectures, making it imperative to precisely understand their complexity requirements. For some objects, it is known that implementations can be significantly more efficient when their usage is restricted. However, apart from the specific restriction of one-shot implementations, where each process may apply only a single operation to the object, very little is known about the complexities of objects under general restrictions.\u0000 This paper draws a more complete picture by defining a large class of objects for which an operation applied to the object can be \"perturbed\" L consecutive times, and proving lower bounds on the time and space complexity of deterministic implementations of such objects. This class includes bounded-value max registers, limited-use approximate and exact counters, and limited-use collect and compare-and-swap objects; L depends on the number of times the object can be accessed or the maximum value it supports.\u0000 For implementations that use only historyless primitives, we prove lower bounds of Omega(min(log L, n)) on the worst-case step complexity of an operation, where n is the number of processes; we also prove lower bounds of Omega( min( L, n )) on the space complexity of these objects. When arbitrary primitives can be used, we prove that either some operation incurs Omega( min( log L, n)) memory stalls or some operation performs Omega( min( log L, n)) steps.\u0000 In addition to these deterministic lower bounds, the paper establishes a lower bound on the expected step complexity of restricted-use randomized approximate counting in a weak oblivious adversary model.","PeriodicalId":367373,"journal":{"name":"ACM Symposium on Parallelism in Algorithms and Architectures","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124137459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Time vs. space trade-offs for rendezvous in trees 在树上集合的时间和空间权衡

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312007

J. Czyzowicz, A. Kosowski, A. Pelc

引用次数: 11

Brief announcement: a GPU accelerated iterated local search TSP solver 简短公告:GPU加速迭代局部搜索TSP求解器

ACM Symposium on Parallelism in Algorithms and Architectures Pub Date : 2012-06-25 DOI: 10.1145/2312005.2312041

K. Rocki, R. Suda

引用次数: 2