Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems最新文献

Continuous-time analog defuzzifier for product-sum based implementations 基于积和实现的连续时间模拟去模糊器

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593727

I. Rojas, F. Pelayo, M. Anguita, A. Prieto

引用次数: 1

VLSI design of radial functions hardware generator for neural computations 神经计算径向函数硬件生成器的VLSI设计

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593717

P. Maffezzoni, P. Gubian

引用次数: 6

Measurement results of the DTCNN-universal chip dtcnn -通用芯片的测量结果

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593211

H. Harrer, J. Nossek, T. Roska, L. Chua

引用次数: 0

VLSI implementation of a modular and programmable neural architecture VLSI实现了模块化和可编程的神经结构

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593713

G. Cardarilli, C. D'Alessandro, P. Marinucci, F. Bordoni

{"title":"VLSI implementation of a modular and programmable neural architecture","authors":"G. Cardarilli, C. D'Alessandro, P. Marinucci, F. Bordoni","doi":"10.1109/ICMNN.1994.593713","DOIUrl":"https://doi.org/10.1109/ICMNN.1994.593713","url":null,"abstract":"A mixed-signal VLSI chip architecture for multi-layer feedforward neural network implementation with digitally programmable synapses is presented. The chip realizes a fully connected single-layer network, configurable as a 48 input/48 output neurons with 2304 5-bit synapses or as a 24 input/24 output neurons with 1152 9-bit synapses. This single layer network can be reconfigured as a multi-layer network. Another important chip feature is the possibility of connecting the chips in order to obtain a more complex multi-layer neural network. The core of the authors' architecture is a very efficient circuit block, \"distributed sigmoid-synapse\", that they used to implement each of the 2304 5-bit synapses included in the programmable neural network. A prototyping chip, including all the basic block of neural architecture, is now processed by ES2 with 1.0 /spl mu/m CMOS technology. Finally, the authors report the architecture of a possible system for the evaluation of the VLSI chip performances. Parameter mismatches present in the chip were considered to be not critical because it is possible to account them during the training of the neural network by using a special chip-in-the-loop training algorithm. The authors planned to use this chip in pattern recognition and image processing applications.","PeriodicalId":366125,"journal":{"name":"Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129201579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

TOTEM: a digital processor for neural networks and Reactive Tabu Search 用于神经网络和反应性禁忌搜索的数字处理器

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593147

R. Battiti, P. Lee, A. Sartori, G. Tecchiolli

引用次数: 15

Analog VLSI cellular fuzzy automata networks for relaxation labeling 用于松弛标记的模拟VLSI细胞模糊自动机网络

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593252

G. Privat, K. Goser

引用次数: 2

Systolic modular VLSI architecture for multi-model neural network implementation 用于多模型神经网络实现的收缩模块化VLSI架构

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593229

J. Moreno, J. Madrenas, J. Cabestany

引用次数: 4

A digital implementation of self-organizing maps 自组织地图的数字实现

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593718

B. Pino, F. Pelayo, A. Prieto

引用次数: 9

Optoelectronic analog antecedent and consequent fuzzy inference units using LED arrays and position sensing devices 采用LED阵列和位置传感装置的光电模拟前后模糊推理单元

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593729

H. Itoh, M. Watanabe, S. Mukai, T. Yamada, S. Uekusa

引用次数: 0

Massively parallel VLSI-implementation of a dedicated neural network for anomaly detection in automated visual quality control 自动化视觉质量控制中异常检测专用神经网络的大规模并行vlsi实现

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems Pub Date : 1994-09-26 DOI: 10.1109/ICMNN.1994.593731

A. Konig, P. Windirsch, M. Glesner

{"title":"Massively parallel VLSI-implementation of a dedicated neural network for anomaly detection in automated visual quality control","authors":"A. Konig, P. Windirsch, M. Glesner","doi":"10.1109/ICMNN.1994.593731","DOIUrl":"https://doi.org/10.1109/ICMNN.1994.593731","url":null,"abstract":"In this work we will present the VLSI-implementation of a dedicated neural network architecture which we have developed in prior work for anomaly detection in automated visual industrial quality control. The network, denoted as NOVAS performs a filtering of inspection images and highlights defects or anomalies in an isomorphic image representation, allowing the detection and localisation of faults on objects. Training of NOVAS is achieved by simply presenting a set of tolerable objects to the network in a single sweep. NOVAS works with single and with multichannel image representations. The processing principle of NOVAS is closely related to nearest neighbor and hypersphere classifier approaches. We have designed an ASIC for the efficient implementation of the nearest neighbor search. Based on that ASIC we will present an architecture of a modular massively parallel computer suited to meet the real-time constraints of manufacturing processes. Further we will report on the status of a prototype system which is close to completion.","PeriodicalId":366125,"journal":{"name":"Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125390869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6