2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)最新文献

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2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2022-09-05 DOI: 10.1109/DISCS.2014.2

引用次数: 0

Replication-aware leakage management in chip multiprocessors with private L2 caches 带有私有L2缓存的芯片多处理器中的复制感知泄漏管理

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840874

Hyunhee Kim, Jung Ho Ahn, Jihong Kim

{"title":"Replication-aware leakage management in chip multiprocessors with private L2 caches","authors":"Hyunhee Kim, Jung Ho Ahn, Jihong Kim","doi":"10.1145/1840845.1840874","DOIUrl":"https://doi.org/10.1145/1840845.1840874","url":null,"abstract":"Power dissipation has become a critical issue in modern chip multiprocessors (CMPs). Managing the leakage power of their L2 caches is particularly important in realizing low-power CMPs because most CMPs employ large L2 caches to hide the performance gap between processors and an off-chip memory while leakage power becomes a major portion in the total power dissipation of CMPs as process technology advances below 90 nm. We propose a replication-aware leakage management technique that selectively turns off a replicated block in a private L2 cache for leakage power reduction. Once a cache line is turned off, the data is lost, but its tag maintains the coherence state. The cost of an extra cache miss due to the turned-off replication is limited since the data of the cache line exists in another on-chip cache. Furthermore, the replicated block incurs no overhead if it is invalidated by other processors in order to maintain cache coherence. Our proposed technique can be implemented by slightly modifying the MESI protocol with a new turned-off shared coherence state. This state indicates that the corresponding block is shared by other caches but turned off. Experiments on a 4 processor CMP with private L2 caches show that the proposed technique reduces the energy consumption of the L2 caches and main memory by 20.0% on average without introducing significant performance loss over the existing cache leakage management technique.","PeriodicalId":363131,"journal":{"name":"2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)","volume":"82 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120807664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Leakage minimization using self sensing and thermal management 使用自感和热管理最小化泄漏

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840900

A. Vahdatpour, M. Potkonjak

引用次数: 5

Customizing pattern set for test power reduction via improved X-identification and reordering 定制模式集，通过改进x识别和重新排序来降低测试功率

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840881

S. K. Kumar, S. Kaundinya, Subhadip Kundu, S. Chattopadhyay

引用次数: 11

MODEST: A model for energy estimation under spatio-temporal variability 一个时空变异性下的能量估算模型

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840873

Shrikanth Ganapathy, R. Canal, Antonio González, A. Rubio

{"title":"MODEST: A model for energy estimation under spatio-temporal variability","authors":"Shrikanth Ganapathy, R. Canal, Antonio González, A. Rubio","doi":"10.1145/1840845.1840873","DOIUrl":"https://doi.org/10.1145/1840845.1840873","url":null,"abstract":"Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the problem of energy estimation more dynamic in nature. It is worsened by process induced variations of low level parameters like threshold voltage and channel length. In this paper we present MODEST, a proposal for estimating the static and dynamic energy of caches taking into account spatial variations of physical parameters, temporal changes of supply voltage and environmental factors like temperature. It can be used to estimate the energy of different blocks of a cache based on a combination empirical data and analytical equations. The observed maximum and median error between MODEST and HSPICE energy-estimates for 22,500 samples is around 7.8% and 0.5% respectively. As a case study, using MODEST, we propose a two step iterative optimization procedure involving Dual-Vth assignment and standby supply voltage minimization for reclaiming energy-constrained caches. The observed energy reduction is around 50.8% for the most-leaky Cache. A speed-up of 750X over conventional hard-coded implementation for such optimizations is achieved.","PeriodicalId":363131,"journal":{"name":"2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116871587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives 探索具有多个设计目标的特定于应用程序的指令集处理器的自定义指令合成

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840875

Hai Lin, Yunsi Fei

引用次数: 4

NBTI-aware DVFS: A new approach to saving energy and increasing processor lifetime nbti感知的DVFS:一种节能和延长处理器寿命的新方法

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840898

M. Basoglu, M. Orshansky, M. Erez

引用次数: 99

Wakeup synthesis and its buffered tree construction for power gating circuit designs 用于电源门控电路设计的唤醒合成及其缓冲树结构

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840936

Seungwhun Paik, Sangmin Kim, Youngsoo Shin

{"title":"Wakeup synthesis and its buffered tree construction for power gating circuit designs","authors":"Seungwhun Paik, Sangmin Kim, Youngsoo Shin","doi":"10.1145/1840845.1840936","DOIUrl":"https://doi.org/10.1145/1840845.1840936","url":null,"abstract":"A power gating circuit suffers from large amount of rush current when it wakes up, especially when all switch cells are turned on at the same time. If each switch cell is turned on in different instant of time, the rush current can be reduced. It is shown in this paper that the rush current can be reduced even more if signal transition time (or signal slew) to each switch cell is adjusted. The wakeup synthesis that we define is to determine the turn-on time and signal slew of each switch cell; the goal is to minimize wakeup delay while rush current is kept below the maximum value that is allowed. The corresponding synthesis algorithm is proposed. The determined turn-on time and signal slew are implemented using a buffered tree, where a source is a wakeup signal and sinks are multiple switch cells; the synthesis algorithm to generate the tree is proposed. The wakeup synthesis and buffered tree construction are integrated into a design flow that receives a netlist of power gating circuit as an input and produces a layout of netlist with wakeup network embedded. Experiments in an industrial 1.1 V, 45-nm technology demonstrate that the wakeup delay is reduced by 43% on average of example circuits compared with 2-pass turn-on, which is widely used.","PeriodicalId":363131,"journal":{"name":"2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128742204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits 原位功率监测方案及其在数字CMOS集成电路动态电压和阈值缩放中的应用

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840899

N. Mehta, G. Naik, B. Amrutur

引用次数: 11

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection 基于低功耗小波变换的癫痫发作检测准平均算法与体系结构

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED) Pub Date : 2010-08-18 DOI: 10.1145/1840845.1840907

Himanshu Markandeya, G. Karakonstantis, S. Raghunathan, P. Irazoqui, K. Roy

引用次数: 17