{"title":"Synchronizing and optimizing multimedia communication with fuzzy clocks","authors":"J. Peters, S. Ramanna","doi":"10.1109/CCECE.1997.614831","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614831","url":null,"abstract":"An extension of the Yang-Huang Real-Time Synchronization Model (RTSM) based on fuzzy clocks is introduced (C.-C. Yang and J.-H. Huang, 1994). For ease of implementation of the fuzzy Real-Time Synchronization Model (fRTSM), timed hierarchical colored Petri nets (HCPNs) labeled with Occam code are used. The focus of the timed HCPN model for fuzzy real time synchronization of networked multimedia communication is in terms of adjusting the timer used in preserving prescribed a priori temporal relationships in the data for multimedia presentations and optimizing the use of network by a source of media data. Contribution of the fuzzy Real-Time Synchronization Model for multimedia communication is its selection of optional work in a multimedia presentation based on the output of a fuzzy clock. A basis for optimized allocation of network bandwidth to senders of multimedia presentations is also built into the fRTSM.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127787966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A shipboard system for remote real-time data collection and monitoring","authors":"J. Millan","doi":"10.1109/CCECE.1997.608376","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608376","url":null,"abstract":"This paper describes a system for collecting data from a ship utilising the MSAT mobile satellite communications network. The system was extensively tested during the period from January-March 1997 on board a Canadian Coast Guard vessel. The results of these tests and future enhancements to the system are presented in this paper.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124361627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A binary multi-level voltage-source inverter for static VAr generation","authors":"S. H. Hosseini, R. Mathur","doi":"10.1109/CCECE.1997.608249","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608249","url":null,"abstract":"In this paper, a new binary multi-level voltage-source inverter (BMVSI) with separate DC sources for high-voltage, high power applications is introduced, which can be used for the dynamic compensation and real-time control of power flow in transmission and distribution systems. The new M-level inverter, where M is 2/sup n+1/-1, consists of only n single-phase full bridges for each phase, in which each bridge has its own separate DC source. This inverter can generate an almost sinusoidal voltage waveform. It employs the least number of components and also is modular in design.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124391782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A survey of the application of AI in capacitor allocation and control","authors":"H. Ng, M. Salama, A. Chikhani","doi":"10.1109/CCECE.1997.614815","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614815","url":null,"abstract":"The installation of power capacitors in distribution systems yields numerous economical benefits and improvements in system performance. There are many algorithms to determine the optimal capacitor sizes and their placement in distribution systems. A majority of the research in this area has used analytical or numerical methods to determine solutions for the optimal capacitor allocation problem. With the growing popularity of artificial intelligence (AI), and availability of AI software packages, several researchers have applied AI techniques to determine optimal capacitor allocation and control. The paper is a critical survey of such techniques including neural networks, genetic algorithms, expert systems, and fuzzy set theory.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131554283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fuzzy neural networks for edge detection","authors":"S. Lu, Ziqing Wang","doi":"10.1109/CCECE.1997.608254","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608254","url":null,"abstract":"Fuzzy neural networks are designed to detect edges. The research comprises two stages: (1) adaptive fuzzification and (2) detection. The fuzzy neural network consists of three layers of neurons. The first layer is an input layer which is divided into eight groups corresponding to blocks in the input pattern. Hence, the structure information in the input pattern is fully utilized. The second layer in the network is used to measure the certainty of the classification for each block. The output layer provides the final measurement of classification. The proposed fuzzy neural network is trained by typical patterns to enable it to determine the edge elements with eight orientations. Pixels having high edge membership are traced and assembled into one picture. The fuzzification, detection, and tracing algorithm are tested. The fuzzy neural network is simulated on a SUN Sparc station. Comparisons are made with a standard edge detection technique. The proposed method obtains a very good result.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131344265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Juanatey, C. Marcano, E. Pernua, T. Adrian, F. D'Alvano, M. Stefanelli
{"title":"Hybrid schemes simulation for ATM flow control","authors":"M. Juanatey, C. Marcano, E. Pernua, T. Adrian, F. D'Alvano, M. Stefanelli","doi":"10.1109/CCECE.1997.608301","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608301","url":null,"abstract":"Flow control is one of the mechanisms employed to prevent and manage the congestion in ATM networks. Rate-based flow control and credit-based flow control are the two best known schemes. None of those mechanisms satisfies entirely the requirements of flow control for LAN and WAN environments simultaneously, but each one has key advantages. This situation originated proposals for integrated rate-credit mechanisms as an alternative for operation in different environments. The objective of this work is to implement and evaluate, through simulation, two of the proposed hybrid mechanisms: credit optional and validity count.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"16 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120902257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA reconfigurability in the presence of logic and I/O faults","authors":"H. Ho, V. Szwarc, T. Kwasniewski","doi":"10.1109/CCECE.1997.608347","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608347","url":null,"abstract":"The SRAM FPGA's reconfigurability is investigated with a view to addressing the problems of reparability through the utilization of a device's unused logic and routing resources. This is done by remapping the design such that the faulty logic is bypassed. This paper addresses the issue of mapping designs onto FPGAs with single and multiple logic and I/O block faults subject to the constraint that the faults are correctly identified, localized, and excluded from the pool of available logic and I/O cells. The viability of the proposed approach depends on the maintenance, within acceptable performance parameters, of the reconfigured circuit's throughput and interface characteristics. The reconfigurability of representative complex butterfly circuit in the presence of single and multiple faults is considered and relevant simulation results based on the ORCA 2C40 device are presented.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123099925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Coding and modulation for mobile satellite systems","authors":"R. Liyanapathirana, H.C. Wiratno","doi":"10.1109/CCECE.1997.614798","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614798","url":null,"abstract":"Mobile satellite systems (MSS) will play an important role in the emerging integrated global communication networks providing personal communication services (PCS). Their coverage will allow mobile communication from anywhere at anytime to rural subscribers as well as to maritime and aeronautical mobile users. In this paper we present an overview of the channel model, and coding and modulation techniques for mobile satellite systems while highlighting the coding aspects relevant to data communication using bandwidth-efficient continuous-phase modulation (CPM).","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129944283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Harmonic distortion in switched-current memory cell","authors":"B. Raahemi, A. Opal","doi":"10.1109/CCECE.1997.608277","DOIUrl":"https://doi.org/10.1109/CCECE.1997.608277","url":null,"abstract":"The lower and upper bounds on the Total Harmonic Distortion (THD) of a switched-current (SI) memory cell are given. The upper bound is an improvement on previously published results. The simulation results show that the THD measure is always within the bounds given by the explicit formula.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Discrete planar electrode dielectrophoresis systems","authors":"L. Hartley, K. Kaler, J. Luo, R. Paul","doi":"10.1109/CCECE.1997.614821","DOIUrl":"https://doi.org/10.1109/CCECE.1997.614821","url":null,"abstract":"Microelectronic based particle processing systems can significantly contribute to advances in a variety of scientific and medical research areas. The ability to characterize and manipulate individual or related groups of particles finds application in areas including chemical processing, imaging, micro system assembly and biological sciences. Planar electrode dielectrophoresis seeks to exploit batch fabrication and MEMS technologies to yield reliable and cost effective particle manipulators. Combinations of these units integrated into self contained particle processing systems will operate on particles in ways reminiscent of how a CPU manipulates digital data. For example, elemental blocks resembling memory, shift registers and A/D converters can be envisioned. Such particle processors may be useful in applications such as blood processing, genetics, tar-sand extraction, thin-film deposition, micro-pore membrane formation and MEMS assembly.","PeriodicalId":359446,"journal":{"name":"CCECE '97. Canadian Conference on Electrical and Computer Engineering. Engineering Innovation: Voyage of Discovery. Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133806068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}