2007 IEEE International Performance, Computing, and Communications Conference最新文献_第4页

Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study 英特尔和AMD双核处理器的内存性能和可扩展性:一个案例研究

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358879

Lu Peng, J. Peir, T. K. Prakash, Yen-kuang Chen, David M. Koppelman

{"title":"Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study","authors":"Lu Peng, J. Peir, T. K. Prakash, Yen-kuang Chen, David M. Koppelman","doi":"10.1109/PCCC.2007.358879","DOIUrl":"https://doi.org/10.1109/PCCC.2007.358879","url":null,"abstract":"As chip multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, performance studies on an Intel Core 2 Duo, an Intel Pentium D and an AMD Athlon 64times2 processor are reported. According to the design specifications, key derivations exist in the critical memory hierarchy architecture among these dual-core processors. In addition to the overall execution time and throughput measurement using both multiprogrammed and multi-threaded workloads, this paper provides detailed analysis on the memory hierarchy performance and on the performance scalability between single and dual cores. Our results indicate that for the best performance and scalability, it is important to have (1) fast cache-to-cache communication, (2) large L2 or shared capacity, (3) fast L2 to core latency, and (4) fair cache resource sharing. Three dual-core processors that we studied have shown benefits of some of these factors, but not all of them. Core 2 Duo has the best performance for most of the workloads because of its microarchitecture features such as shared L2 cache. Pentium D shows the worst performance in many aspects due to its technology-remap of Pentium 4.","PeriodicalId":356565,"journal":{"name":"2007 IEEE International Performance, Computing, and Communications Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132350188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

CT-RBAC: A Temporal RBAC Model with Conditional Periodic Time CT-RBAC:一个具有条件周期时间的时间RBAC模型

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358928

Kai Ouyang, J. Joshi

{"title":"CT-RBAC: A Temporal RBAC Model with Conditional Periodic Time","authors":"Kai Ouyang, J. Joshi","doi":"10.1109/PCCC.2007.358928","DOIUrl":"https://doi.org/10.1109/PCCC.2007.358928","url":null,"abstract":"Many emerging applications show the need for a fine-grained context based access control requirements. The generalized temporal RBAC model has been proposed to capture fine-grained time-based access control requirements using periodic time expression to capture recurring intervals of time. In this paper, we present conditional temporal RBAC (CT-RBAC) model that extends GTRBAC model by extending the periodic time expression. In particular, the extension allows fine-grained extension to capture other logical conditions that restricts the validity of the temporal constraints. CT-RBAC uses a symbolic representation of conditional periodic time that can be used to define a set of conditions to qualify the components of a periodic time expression, using the concurrent transaction logic. Because of the conditional set introduced, CT-RBAC extends the time control dimension to the (condition, time) control plane and the (time, constraint) plane of the GTRBAC framework to the (condition, time, constraint) three-dimensional control space, thus providing more flexibility in the access control model. We analyze conflicts introduced by the constraint set and the complexity of evaluating the conditional set.","PeriodicalId":356565,"journal":{"name":"2007 IEEE International Performance, Computing, and Communications Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114722793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Parallelizing Protocol Processing on SMT Processor Efficiently: A FSM Decomposition Approach SMT处理器上高效并行协议处理:一种FSM分解方法

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358913

Zhibin Zhang, Li Guo, Binxing Fang, Xiaojun Chen

{"title":"Parallelizing Protocol Processing on SMT Processor Efficiently: A FSM Decomposition Approach","authors":"Zhibin Zhang, Li Guo, Binxing Fang, Xiaojun Chen","doi":"10.1109/PCCC.2007.358913","DOIUrl":"https://doi.org/10.1109/PCCC.2007.358913","url":null,"abstract":"With the increase of network bandwidth, high performance protocol processing plays more and more important role in high speed network security. Recent studies show that current computer architecture advances and CPU performance improvements have limited impact on network protocol processing performance. Some studies find that in real SMT processor like Intel Xeon processor with hyper-threadings, the sharing resources (like cache) contention between threads can hurt the processing performance of network applications like servers or IDS. How to make protocol processing cope with the advances in computer architecture has been widely studied. In this paper, we put our focus on the processing performance of TCP automata phases, using execution based simulations to model the relationship between each phase performance and cache size, and then measuring the cache contention between threads. We find (1) the load/store units can be the bottleneck of protocol processing; and (2) in connection establishing phase of TCP processing, cache contention between threads is more aggressive than any other phase. We also suggest a FSM decomposition based parallel processing approach to use sharing cache of SMT processors effectively.","PeriodicalId":356565,"journal":{"name":"2007 IEEE International Performance, Computing, and Communications Conference","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133044535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

First Responders' Crystal Ball: How to Scry the Emergency from a Remote Vehicle 第一响应者的水晶球:如何从远程车辆预测紧急情况

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358940

M. Roccetti, M. Gerla, C. Palazzi, S. Ferretti, G. Pau

引用次数: 53

How to Assign Traffic Sources to Nodes in Disaster Area Scenarios 灾备场景下如何为节点分配流量源

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358906

N. Aschenbruck, P. Martini, M. Gerharz

引用次数: 6

A Reliable Wireless Mesh Infrastructure Deployment at Crisis Site 危机现场可靠的无线网状基础设施部署

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358944

R. Dilmaghani, R. Rao

引用次数: 1

On Network Coding Based Multirate Video Streaming in Directed Networks 有向网络中基于网络编码的多速率视频流

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358911

Xu Chenguang, X. Yinlong, Zhan Cheng, Wu Ruizhe, Wang Qingshan

引用次数: 29

Analysis of Queuing Delay in RPR Networks RPR网络中的排队延迟分析

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358888

B. Hariri, Mohammadreza Pakravan

引用次数: 0

PID: A Queue Management Scheme for Improving Network Resilience Under Worm Attacks PID:一种提高蠕虫攻击下网络弹性的队列管理方案

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358932

Jintao Xiong

引用次数: 1

Understanding Localized-Scanning Worms 了解本地化扫描蠕虫

2007 IEEE International Performance, Computing, and Communications Conference Pub Date : 2007-04-11 DOI: 10.1109/PCCC.2007.358894

Zesheng Chen, Chao-Yu Chen, C. Ji

引用次数: 39