2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)最新文献_第3页

ILPc: A novel approach for scalable timing analysis of synchronous programs ILPc:同步程序可扩展时序分析的新方法

2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Pub Date : 2013-09-29 DOI: 10.1109/CASES.2013.6662526

J. Wang, P. Roop, Sidharta Andalam

{"title":"ILPc: A novel approach for scalable timing analysis of synchronous programs","authors":"J. Wang, P. Roop, Sidharta Andalam","doi":"10.1109/CASES.2013.6662526","DOIUrl":"https://doi.org/10.1109/CASES.2013.6662526","url":null,"abstract":"Synchronous programs have been widely used in the design of safety critical systems such as the flight control of Airbus A-380. To validate the implementations of synchronous programs, it is necessary to map the program's logical time (measured in logical ticks) to physical time (the execution time on a given processor). The static computation of the worst case execution time of logical ticks is called Worst Case Reaction Time (WCRT) analysis. Several approaches for WCRT analysis exist: max-plus algebra, model checking, reachability and integer linear programming (ILP). Of these approaches, reachability, model checking and ILP provide reasonably precise worst case estimates at the expense of longer analysis time. Apart from max-plus based approaches, which can produce large overestimates, the existing approaches suffer from the state space explosion problem. In this paper, we develop a new ILP based approach, called ILPc-which exploits the concurrency explicitly in the ILP formulation to avoid the state space explosion problem. Through extensive bench-marking we demonstrate the efficacy of the approach: for complex programs, ILPc is often orders of magnitude faster compared to the existing approaches, while achieving same level of precision. Thus, this paper paves the way for scalable WCRT analysis of complex embedded systems designed using the synchronous approach.","PeriodicalId":354180,"journal":{"name":"2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126650050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator 用于3d堆叠可重构加速器的混合编译和运行时内存管理

2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Pub Date : 2013-09-29 DOI: 10.1109/CASES.2013.6662514

L. Gauthier, Shinya Ueno, Koji Inoue

引用次数: 0

Minimizing code size via page selection optimization on partitioned memory architectures 通过在分区内存架构上优化页面选择来最小化代码大小

2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Pub Date : 2013-09-29 DOI: 10.1109/CASES.2013.6662516

Mengting Yuan, C. Xue, Chen Yong, Qing'an Li, Yingchao Zhao

{"title":"Minimizing code size via page selection optimization on partitioned memory architectures","authors":"Mengting Yuan, C. Xue, Chen Yong, Qing'an Li, Yingchao Zhao","doi":"10.1109/CASES.2013.6662516","DOIUrl":"https://doi.org/10.1109/CASES.2013.6662516","url":null,"abstract":"For 8-bit microcontrollers, bank-switching is commonly used to increase memory capacity. The disadvantage of this technique is that bank (page) selection instructions are introduced when switching active data (program) bank. The page selection problem is to minimize the number of page selection instructions inserted. While previous efforts work on optimizing bank selection instructions for the data segment, our work focuses on minimizing page selection instructions for the program segment. Minimizing page selection instructions is a more challenging problem as the size of each procedure being allocated is affected by the number of inserted page selection instructions. In this paper, we first give a formal definition of the page selection problem, and then we formulate the problem as an Integer Linear Programming (ILP) to find the optimal solution. We introduce a tabu search heuristic algorithm, TMSEARCH, to solve the problem efficiently. The experimental results show that ILP can find optimal solutions for small-scale problems, and TMSEARCH is able to find good solutions for all benchmarks within reasonable time. Com-pared to a commercial compiler, TMSEARCH reduces total code size between 0.04% and 19.3%, and reduces page selection instructions between 24.3% and 78.7%.","PeriodicalId":354180,"journal":{"name":"2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platforms 嵌入式异构多核平台管道并行度的自动提取

2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Pub Date : 2013-09-29 DOI: 10.1109/CASES.2013.6662508

D. Cordes, M. Engel, Olaf Neugebauer, P. Marwedel

{"title":"Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platforms","authors":"D. Cordes, M. Engel, Olaf Neugebauer, P. Marwedel","doi":"10.1109/CASES.2013.6662508","DOIUrl":"https://doi.org/10.1109/CASES.2013.6662508","url":null,"abstract":"Automatic parallelization of sequential applications is the key for efficient use and optimization of current and future embedded multi-core systems. However, existing approaches often fail to achieve efficient balancing of tasks running on heterogeneous cores of an MPSoC. A reason for this is often insufficient knowledge of the underlying architecture's performance. In this paper, we present a novel parallelization approach for embedded MPSoCs that combines pipeline parallelization for loops with knowledge about different execution times for tasks on cores with different performance properties. Using Integer Linear Programming, an optimal solution with respect to the model used is derived implementing tasks with a well-balanced execution behavior. We evaluate our pipeline parallelization approach for heterogeneous MPSoCs using a set of standard embedded benchmarks and compare it with two existing state-of-the-art approaches. For all benchmarks, our parallelization approach obtains significantly higher speedups than either approach on heterogeneous MPSoCs.","PeriodicalId":354180,"journal":{"name":"2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126880220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18