2017 27th International Conference on Field Programmable Logic and Applications (FPL)最新文献

A security library for FPGA interlays FPGA互连层的安全库

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-10-05 DOI: 10.23919/FPL.2017.8056817

Anuj Vaishnav, J. Ordaz, Dirk Koch

引用次数: 3

Body bias optimization for variable pipelined CGRA 可变流水线CGRA的体偏置优化

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-10-02 DOI: 10.23919/FPL.2017.8056851

Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, H. Amano

{"title":"Body bias optimization for variable pipelined CGRA","authors":"Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, H. Amano","doi":"10.23919/FPL.2017.8056851","DOIUrl":"https://doi.org/10.23919/FPL.2017.8056851","url":null,"abstract":"Variable Pipeline Cool Mega Array (VPCMA) is an low power Coarse Grained Reconfigurable Architecture (CGRA) based on the concept of CMA (Cool Mega Array). It implements a pipeline structure that can be configured depending on performance requirements, and the silicon on thin buried oxide (SOTB) technology that allows to control its body bias voltage to balance performance and leakage power. In this paper, we propose a methodology to optimize exactly with an Integer Linear Program the VPCMA body bias while considering simultaneously its variable pipeline structure. For the studied applications, we evaluate that it is possible to achieve an average reduction of energy consumption of 19.3% and 11.8% when compared to respectively the zero bias (without body bias control) and the uniform (control of the whole PE array) cases, while respecting performance constraints. Besides, with appropriate body bias control, it is possible to extend the possible performance, hence enabling broader trade-off analyzes between consumption and performance. These promising results show that applying an adequate optimization technique for the body bias control while simultaneously considering pipeline structures can not only enable further power reduction than previous methods, but also allow more trade-off analysis possibilities.","PeriodicalId":353285,"journal":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132067676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

In-switch approximate processing: Delayed tasks management for MapReduce applications 交换中近似处理:MapReduce应用程序的延迟任务管理

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-10-02 DOI: 10.23919/FPL.2017.8056802

Koya Mitsuzuka, Ami Hayashi, M. Koibuchi, H. Amano, Hiroki Matsutani

{"title":"In-switch approximate processing: Delayed tasks management for MapReduce applications","authors":"Koya Mitsuzuka, Ami Hayashi, M. Koibuchi, H. Amano, Hiroki Matsutani","doi":"10.23919/FPL.2017.8056802","DOIUrl":"https://doi.org/10.23919/FPL.2017.8056802","url":null,"abstract":"In MapReduce, the parallel processing performance is often limited by only a few compute nodes that delay to complete given tasks. Although various techniques have been invented to handle such stragglers, these techniques mostly impose a burden on master node to monitor the progress of all the compute nodes, resulting in a new bottleneck as the number of compute nodes increases. As an alternative approach, in this paper, we propose to move such straggler management burden from master node to network switch that connects the master and compute nodes, because all the information goes through the switch. More specifically, the proposed network switch monitors output packets from Map tasks to detect stragglers. When detected, the proposed switch generates a response instead of the straggler based on the outputs of the other normal Map tasks, so that Reduce tasks can be started without delay. We introduce some approximate techniques for the proxy computation and response at the switch; thus our switch is called \"ApproxSW.\" We implement ApproxSW on NetFPGA-SUME board that has four 10Gbit Ethernet (10GbE) interfaces and a Virtex-7 FPGA. An experiment shows that the ApproxSW functions do not degrade the original 10GbE switch performance. We also analyze the accuracy of the proxy computation and response for stragglers and show that the proposed approximation based on task similarity achieves the best accuracy.","PeriodicalId":353285,"journal":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132117497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA 交换加速器:用于紧耦合交换集线器和带有FPGA的加速器的框架

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-10-02 DOI: 10.23919/FPL.2017.8056846

Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, H. Amano

{"title":"Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA","authors":"Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, H. Amano","doi":"10.23919/FPL.2017.8056846","DOIUrl":"https://doi.org/10.23919/FPL.2017.8056846","url":null,"abstract":"Accelerator-in-Switch (AiS) is a framework for building an accelerator logic tightly coupled with a switching hub in a single FPGA for high performance computation with heterogeneous environment with CPUs and GPUs. AiS is implemented on a partial reconfigurable region of an FPGA whose permanent region is used for a switching hub. A port of the switching hub is connected to the registers and local memory of AiS directly. AiS has a standard interface for a standard bus (Avalon MM bus, here) to exchange data between on-board DDR SDRAM and the local memory, and various types of accelerators can be implemented just by providing such an interface. The data input and output are performed with the DMA controller inside the switching hub with the shared memory model between host CPUs and GPUs. We implemented two example accelerators: a reduction calculator for a radiation transfer equations solver (RED) and LET generator for N-body simulation (LET) were implemented as the AiS on PEACH3, a switching hub for a PCIe direct interconnection network with Altera's Stratix V. The use of partial reconfiguration makes it possible to switch multiple accelerators without stopping the switching hub. As a result, we reduced the time for place&route of an accelerator by 47% compared to the case of the design combining the accelerator into the switching hub.","PeriodicalId":353285,"journal":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115579868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN 一种新的基于fpga的轨道重建方法，用于CERN CMS实验的一级触发

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-10-02 DOI: 10.23919/FPL.2017.8056825

R. Aggleton, L. Ardila-Perez, F. Ball, M. Balzer, J. Brooke, L. Calligaris, M. Caselle, D. Cieri, E. Clement, G. Hall, K. Harder, P. Hobson, G. Iles, T. James, K. Manolopoulos, T. Matsushita, A. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. Reid, A. Rose, O. Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber

{"title":"A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN","authors":"R. Aggleton, L. Ardila-Perez, F. Ball, M. Balzer, J. Brooke, L. Calligaris, M. Caselle, D. Cieri, E. Clement, G. Hall, K. Harder, P. Hobson, G. Iles, T. James, K. Manolopoulos, T. Matsushita, A. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. Reid, A. Rose, O. Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber","doi":"10.23919/FPL.2017.8056825","DOIUrl":"https://doi.org/10.23919/FPL.2017.8056825","url":null,"abstract":"The Compact Muon Solenoid (CMS) experiment at CERN is scheduled for a major upgrade in the next decade in order to meet the demands of the new High Luminosity Large Hadron Collider. Amongst others, a new tracking system is under development including an outer tracker capable of rejecting low transverse momentum particles by looking at the coincidences of hits (stubs) in two closely spaced sensor layers in the same tracker module. Accepted stubs are transmitted off-detector for further processing at 40 MHz. In order to maintain under the increased luminosity the Level-1 trigger rate at 750 kHz, tracker data need to be included in the decision making process. For this purpose, a system architecture has to be developed that will be able to identify particles with transverse momentum above 3 GeV/c by building tracks out of stubs, while achieving an overall processing latency of maximum 4us. Targeting these requirements the current paper presents an FPGA-based track finding architecture that identifies track candidates in real-time and bases its functionality on a fully time-multiplexed approach. As a proof of concept, a hardware system has been assembled targeting the MP7 MicroTCA processing card that features a Xilinx Virtex-7 FPGA, demonstrating a realistic slice of the track finder. The paper discusses the algorithms' implementation and the efficient utilisation of the available FPGA resources, it outlines the system architecture, and presents some of the hardware demonstrator results.","PeriodicalId":353285,"journal":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133378200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

ARMHEx: A hardware extension for DIFT on ARM-based SoCs ARMHEx:基于arm的soc上DIFT的硬件扩展

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-09-04 DOI: 10.23919/FPL.2017.8056767

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapôtre, G. Gogniat

引用次数: 16

ARMHEx: A framework for efficient DIFT in real-world SoCs ARMHEx:一个在实际soc中实现高效DIFT的框架

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-09-04 DOI: 10.23919/FPL.2017.8056799

Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapôtre, G. Gogniat

引用次数: 1

Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations 桥接高级综合和特定应用的算术:浮点求和的案例研究

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-09-04 DOI: 10.23919/FPL.2017.8056792

Yohann Uguen, F. D. Dinechin, Steven Derrien

{"title":"Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations","authors":"Yohann Uguen, F. D. Dinechin, Steven Derrien","doi":"10.23919/FPL.2017.8056792","DOIUrl":"https://doi.org/10.23919/FPL.2017.8056792","url":null,"abstract":"FPGAs are well known for their ability to perform non-standard computations not supported by classical microprocessors. Many libraries of highly customizable application-specific IPs have exploited this capablity. However, using such IPs usually requires handcrafted HDL, hence significant design efforts. High Level Synthesis (HLS) lowers the design effort thanks to the use of C/C++ dialects for programming FPGAs. However, high-level C language becomes a hindrance when one wants to express non-standard computations: this languages was designed for programming microprocessors and carries with it many restrictions due to this paradigm. This is especially true when computing with floating-point, whose data-types and evaluation semantics are defined by the IEEE-754 and C11 standards. If the high-level specification was a computation on the reals, then HLS imposes a very restricted implementation space. This work attempts to bridge FPGA application-specific efficiency and HLS ease of use. It specifically targets the ubiquitous floating-point summation-reduction pattern. A source-to-source compiler transforms selected floating-point additions into sequences of simpler operators using non-standard arithmetic formats. This improves performance and accuracy for several benchmarks, while keeping the ease of use of a high-level C description.","PeriodicalId":353285,"journal":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Quantifying and mitigating the costs of FPGA virtualization 量化和降低FPGA虚拟化的成本

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-09-01 DOI: 10.23919/FPL.2017.8056807

S. Yazdanshenas, Vaughn Betz

{"title":"Quantifying and mitigating the costs of FPGA virtualization","authors":"S. Yazdanshenas, Vaughn Betz","doi":"10.23919/FPL.2017.8056807","DOIUrl":"https://doi.org/10.23919/FPL.2017.8056807","url":null,"abstract":"FPGAs are being incorporated into contemporary datacenters in order to improve computational capacity, power consumption, and processing latency. Efficiently integrating FP-GAs in datacenters is, however, quite challenging. Ideally, smaller tasks could share a device and the cloud management layer would be able to partially reconfigure the device to allocate its free resources to incoming tasks. Moreover, to facilitate FPGA hardware upgrades without undue porting effort for previously developed accelerator tasks, the complexities associated with board-specific system-level integration should be abstracted away from designers. By meeting these requirements, FPGAs in the cloud would become multi-user virtualized resources with increased availability and elasticity. The virtualization of FPGAs, however, comes with two major costs in current FPGAs: lower application operating frequency, and extravagant use of routing resources. In this paper, we quantify the costs of FPGA virtualization and demonstrate that for an FPGA that supports four independent tasks, virtualization reduces the task average frequency by 18% to 46% and increases wire usage to 2.6×. We also investigate the cause of these costs and show that the use of hard NoCs in future datacenter-optimized FPGAs would facilitate FPGA virtualization without sacrificing operating frequency or routing resources.","PeriodicalId":353285,"journal":{"name":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130497152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

On accelerating pair-HMM computations in programmable hardware 可编程硬件中对hmm计算的加速研究

2017 27th International Conference on Field Programmable Logic and Applications (FPL) Pub Date : 2017-09-01 DOI: 10.23919/FPL.2017.8056837

Subho Sankar Banerjee, Mohamed El-Hadedy, C. Y. Tan, Z. Kalbarczyk, S. Lumetta, R. Iyer

引用次数: 18