D. Fitrio, S. Tjoa, Anand Mohan, R. Veljanovski, A. Berry, G. Panjkovic
{"title":"A CMOS analog integrated circuit for pixel X-Ray detector","authors":"D. Fitrio, S. Tjoa, Anand Mohan, R. Veljanovski, A. Berry, G. Panjkovic","doi":"10.1142/S0218126611007086","DOIUrl":"https://doi.org/10.1142/S0218126611007086","url":null,"abstract":"The fabricated analog application specific integrated circuit (ASIC) is a front-end circuit for multichannel pixel detector system. The designed ASIC provides signal amplification for a pixelated arrays of 1 mm and 200µm pitch pixel detectors made from Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CZT) detector. Both the detector and ASIC are combined to target future high intensity research applications for modern X-Ray detector systems. The ASIC was fabricated in a 0.35 µm process by AustriaMicrosystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1mV/KeV of photon energy in the 30–120KeV energy range. The preamplifier and shaper circuit are designed for both electron and hole polarities of the input signals, so that it can be used as anode or cathode readout and this can be optimised via a common bias level control signal. The ASIC's shaper has been designed with a time constant of 100ns to allow operation at photon rate events above 1 Million photons per pixel per second The design and characterisation of the readout chip will be discussed in this paper presenting both simulated and fabricated results from the chip.","PeriodicalId":348978,"journal":{"name":"Proceedings of the 2009 12th International Symposium on Integrated Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124872500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform","authors":"B. K. Mohanty, P. Meher","doi":"10.1109/ICIAS.2007.4658605","DOIUrl":"https://doi.org/10.1109/ICIAS.2007.4658605","url":null,"abstract":"In this paper, we have presented a bit-serial systolic-like architecture for the computation of non-separable two-dimensional discrete wavelet transform (2-D DWT) based on the principle of distributed arithmetic. The computational core of the proposed structure is highly regular and modular. The computations which become redundant due to the decimation process are eliminated to obtain a low-complexity computing algorithm for the 2-D DWT. Moreover, it exploits the advantage of constant wavelet filter-base in the DA-based structure to reduce the hardware-complexity. It is shown that the proposed structure involves very low hardware complexity, and significantly less area-time complexity compared with the existing bit-level designs.","PeriodicalId":348978,"journal":{"name":"Proceedings of the 2009 12th International Symposium on Integrated Circuits","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126831414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}