用于像素x射线探测器的CMOS模拟集成电路

D. Fitrio, S. Tjoa, Anand Mohan, R. Veljanovski, A. Berry, G. Panjkovic
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引用次数: 4

摘要

自制模拟专用集成电路(ASIC)是多通道像素探测系统的前端电路。设计的ASIC为1 mm和200µm间距的像素化阵列碲化镉(CdTe)和碲化镉锌(CZT)探测器提供信号放大。这两个探测器和ASIC相结合的目标是未来高强度的研究应用于现代x射线探测器系统。ASIC由奥地利微系统公司以0.35µm工艺制造,由32个通道组成,其中每个通道包含一个电荷敏感放大器,一个脉冲整形器和两个进一步的放大级,在30-120KeV能量范围内提供1mV/KeV的光子能量总增益。前置放大器和整形电路是为输入信号的电子和空穴极性而设计的,因此它可以用作阳极或阴极读出,这可以通过一个共同的偏置电平控制信号来优化。ASIC的整形器被设计为100ns的时间常数,以允许在超过100万光子每像素每秒的光子速率事件下运行。本文将讨论读出芯片的设计和特性,并给出芯片的模拟和制造结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A CMOS analog integrated circuit for pixel X-Ray detector
The fabricated analog application specific integrated circuit (ASIC) is a front-end circuit for multichannel pixel detector system. The designed ASIC provides signal amplification for a pixelated arrays of 1 mm and 200µm pitch pixel detectors made from Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CZT) detector. Both the detector and ASIC are combined to target future high intensity research applications for modern X-Ray detector systems. The ASIC was fabricated in a 0.35 µm process by AustriaMicrosystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1mV/KeV of photon energy in the 30–120KeV energy range. The preamplifier and shaper circuit are designed for both electron and hole polarities of the input signals, so that it can be used as anode or cathode readout and this can be optimised via a common bias level control signal. The ASIC's shaper has been designed with a time constant of 100ns to allow operation at photon rate events above 1 Million photons per pixel per second The design and characterisation of the readout chip will be discussed in this paper presenting both simulated and fabricated results from the chip.
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