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2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium最新文献

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IMT-Advanced - Objective and Challenges imt高级-目标和挑战
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315814
K. Miyahara
{"title":"IMT-Advanced - Objective and Challenges","authors":"K. Miyahara","doi":"10.1109/CSICS.2009.5315814","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315814","url":null,"abstract":"This paper describes drivers and objectives for IMTAdvanced mobile broadband system defined by ITU-R as well as technical challenges. Keywords-component; IMT-Advanced; LTE; IEEE802.16; WiMAX","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126095517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-Resistivity SOI CMOS Cellular Antenna Switches 高电阻SOI CMOS蜂窝天线开关
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315667
M. Carroll, D. Kerr, C. Iversen, A. Tombak, Jean-Blaise Pierres, P. Mason, J. Costa
{"title":"High-Resistivity SOI CMOS Cellular Antenna Switches","authors":"M. Carroll, D. Kerr, C. Iversen, A. Tombak, Jean-Blaise Pierres, P. Mason, J. Costa","doi":"10.1109/CSICS.2009.5315667","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315667","url":null,"abstract":"Results for cellular antenna switches using high- resistivity silicon-on-insulator (SOI) CMOS technology are presented. The performance of SOI RF switch FETs is presented and compared to a production GaAs pHEMT technology. Data from prototype high-resistivity SOI RF switch designs is presented and compared to pHEMT based designs.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124583007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The Evolution and Importance of Composition in RF Compound Semiconductors 射频化合物半导体中成分的演变及其重要性
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315803
C. Barratt
{"title":"The Evolution and Importance of Composition in RF Compound Semiconductors","authors":"C. Barratt","doi":"10.1109/CSICS.2009.5315803","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315803","url":null,"abstract":"History Compound semiconductors found their origins in the discovery of the transferred electron or “Gunn” effect by J.B. Gunn in 1962 while working at the Royal Signals and Radar Establishment in the UK. This phenomenon provided a net reduction in electron drift velocity with increased electric field at specific carrier concentrations. By utilizing this negative impedance, a transit time device useful as an oscillator could be fabricated. These two terminal devices while called diodes, do not contain a semiconductor junction but when properly designed and placed in a resonant cavity, can produce low efficiency RF energy directly from DC.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116147462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 32-GS/s 6-Bit Double-Sampling DAC in InP HBT Technology 基于InP HBT技术的32gs /s 6位双采样DAC
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315628
M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, K. Murata
{"title":"A 32-GS/s 6-Bit Double-Sampling DAC in InP HBT Technology","authors":"M. Nagatani, H. Nosaka, S. Yamanaka, K. Sano, K. Murata","doi":"10.1109/CSICS.2009.5315628","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315628","url":null,"abstract":"This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for a coherent optical transceiver based on digital signal processing (DSP). To achieve a high sampling rate, a novel double-sampling technique was devised. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. Measured DNL and INL were within +0.49/-0.17 LSB and +0.97/-0.06 LSB, respectively. Measured SFDR was 45.0 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which is the limit of our measurement setup. Ramp-wave output at a sampling rate of 32 GS/s was obtained. Total power consumption was 1.4 W with a supply voltage of -4.0 V. To our knowledge, this is the first 6-bit DAC that can operate at a sampling rate of over 30 GS/s.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"166 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127566370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A Fully Integrated, Compound Transceiver MIMIC Utilizing Six Antenna Ports for 60 GHz Wireless Applications 一种完全集成的复合收发器MIMIC，利用六个天线端口用于60 GHz无线应用
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315785
S. Koch, I. Kallfass, R. Weber, A. Leuther, M. Schlechtweg, S. Saito
{"title":"A Fully Integrated, Compound Transceiver MIMIC Utilizing Six Antenna Ports for 60 GHz Wireless Applications","authors":"S. Koch, I. Kallfass, R. Weber, A. Leuther, M. Schlechtweg, S. Saito","doi":"10.1109/CSICS.2009.5315785","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315785","url":null,"abstract":"A fully integrated transceiver MIMIC (millimeter wave monolithic integrated circuit) with six antenna port functionality for 55 to 65 GHz wireless applications has been developed. The chip has been realized using 100 nm gatelength metamorphic InAlAs / InGaAs HEMT (high electron mobility transistor) technology on GaAs substrates together with CPW (coplanar waveguide) technology. The novel transceiver topology consists of switches, amplifiers, mixers, a voltage controlled oscillator and a frequency divider. The receiver chain shows noise figure < 2.6 dB on the low noise amplifier level and smaller than 7 dB including the antenna switching network. The medium output power amplifier delivers the saturated power level of + 14 dBm. This is the highest integration level for a 60 GHz compound semiconductor transceiver chip reported to-date.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133888668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Passive W-Band Imager in 65nm Bulk CMOS 65nm CMOS无源w波段成像仪
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315696
A. Tomkins, P. Garcia, S. Voinigescu
{"title":"A Passive W-Band Imager in 65nm Bulk CMOS","authors":"A. Tomkins, P. Garcia, S. Voinigescu","doi":"10.1109/CSICS.2009.5315696","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315696","url":null,"abstract":"A passive imager operating in the W-band around 90GHz has been realized in a digital 65nm CMOS process. The imager, occupying only 0.41mm 2 , integrates an SPDT switch with 4.2dB loss and 25dB isolation, a 5-stage telescopic cascode LNA with 27dB gain at 90GHz, and a W-band square-law detector, all consuming less than 33mA from 1.2V. The imager, when measured without the input SPDT, has a peak responsivity of over 200kV/W, and a minimum NEP of less than 0.1pW/√Hz. With the input switch, it achieves a 90kV/W responsivity and an NEP of 0.2pW/√Hz. This receiver represents the highest frequency imager to be implemented in standard CMOS with this level of integration. I. INTRODUCTION W-band imagers are attractive due to their potential for high resolution operation and their ability to penetrate various materials. Typical imagers at these frequencies have been realized using III/V technologies, with InP HEMT LNAs in conjunction with planar doped barrier or Schottky detectors (1). Recent publications have investigated the use of zero-bias backward tunnel diodes (1), and even SiGe HBTs (2). Nanoscale CMOS, as in this paper, represents an opportunity to leverage the economies of scale, and the potentital for large-scale wafer-level integration. A modern CMOS process utilizes 300mm wafers and can potentially permit the integration of thousands of imaging elements on a single wafer.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115033164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Compact and Broadband Millimeter-Wave Mixer Based on the New Phase Relationship 基于新相位关系的小型宽带毫米波混频器
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315646
Yu-Ann Lai, S. Hung, Yeong-Her Wang
{"title":"Compact and Broadband Millimeter-Wave Mixer Based on the New Phase Relationship","authors":"Yu-Ann Lai, S. Hung, Yeong-Her Wang","doi":"10.1109/CSICS.2009.5315646","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315646","url":null,"abstract":"A millimeter-wave monolithic mixer with new phase relationship is demonstrated and fabricated through a 0.25 μm PHEMT process. This mixer is composed of two 900 hybrids with new phase relationships, which provides the function like the 1800 hybrids in the double balanced mixer structure. And it does not only provide flexible layout design, but also offer wideband performance. The measured results demonstrate a conversion loss of 10.2~14.5 dB over 18-40 GHz operation bandwidth, and the 1-dB compression power of 6 dBm at 27 GHz. Moreover, the LO-IF and RF-IF isolation are better than 20dB from 28-40 GHz, and this proposed configuration leads to a die size of less than 0.48 × 0.77 mm. Keywords-Phase relationships, double balanced mixer (DBM), hybrid, PHEMT","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116553765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling of an InGaP/GaAs BiFET VVR Device InGaP/GaAs BiFET VVR器件的建模
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315681
W. Clausen, B. Moser
{"title":"Modeling of an InGaP/GaAs BiFET VVR Device","authors":"W. Clausen, B. Moser","doi":"10.1109/CSICS.2009.5315681","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315681","url":null,"abstract":"A recently introduced InGaP/GaAs BiFET process allows the integration of a JFET device with a standard HBT process. This JFET device, also called a voltage variable resistor (VVR), can be utilized in bias control circuits on the same die as HBT power amplifiers. An innovative modeling solution was developed to simulate temperature and surface state mechanisms related to device performance. For this modeling work, a parasitic FET model is used for surface state effects along with a dual diode model for voltage dependent ideality. Using these techniques, accurate simulations can be made to design near device limitations.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Compact Cascode Power Amplifier in 45-nm CMOS for 60-GHz Wireless Systems 用于60 ghz无线系统的45纳米CMOS紧凑型级联功率放大器
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315699
T. Kjellberg, M. Abbasi, M. Ferndahl, A. de Graauw, E. v. d. Heijden, H. Zirath
{"title":"A Compact Cascode Power Amplifier in 45-nm CMOS for 60-GHz Wireless Systems","authors":"T. Kjellberg, M. Abbasi, M. Ferndahl, A. de Graauw, E. v. d. Heijden, H. Zirath","doi":"10.1109/CSICS.2009.5315699","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315699","url":null,"abstract":"This paper presents a power amplifier in 45nm CMOS technology operating in the 50 to 60-GHz frequency range. It uses a single-ended topology with two cascode stages. A gain of 19.6 dB is obtained at 54 GHz where the gain peaks, and 17 dB at 60 GHz. The measured output-referred 1-dB compression point is 8.7 dBm at 60 GHz and a supply voltage of 2.1 V, and the saturated output power is 13.5 dBm. The bias conditions are shown to be reliable through lifetime measurements. The active chip-area measures 160 mu m x 110 mu m.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"87 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120884478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
GaN Technology for RF Electronics - Development Status in Europe 射频电子GaN技术-欧洲发展现状
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium Pub Date : 2009-11-06 DOI: 10.1109/CSICS.2009.5315810
H. Blanck, J. Splettstosser, D. Floriot
{"title":"GaN Technology for RF Electronics - Development Status in Europe","authors":"H. Blanck, J. Splettstosser, D. Floriot","doi":"10.1109/CSICS.2009.5315810","DOIUrl":"https://doi.org/10.1109/CSICS.2009.5315810","url":null,"abstract":"GaN technology has gained a lot of attention in Europe over the last few years for various domains including RF electronics. This paper will try to summarize the current status achieved and illustrate it with a few representative examples. Due to the importance of the subject this paper will focus solely on the RF electronics related topics, which should be of major interest in the frame of this conference. Aspects covering material, devices up to circuits and module integration will be addressed.","PeriodicalId":347399,"journal":{"name":"2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122995113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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