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2006 IEEE International SOC Conference最新文献

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A 120nm CMOS Fully Differential Rail-to-Rail I/O Opamp with Highly Constant Signal Behavior 具有高度恒定信号行为的120nm CMOS全差分轨对轨I/O运放
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283831
W. Yan, H. Zimmermann
{"title":"A 120nm CMOS Fully Differential Rail-to-Rail I/O Opamp with Highly Constant Signal Behavior","authors":"W. Yan, H. Zimmermann","doi":"10.1109/SOCC.2006.283831","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283831","url":null,"abstract":"This paper proposes a fully differential opamp implemented in 120 nm digital CMOS technology, with rail-to-rail input common-mode range, realized by a novel approach of constant small- and large-signal behavior control. The small-signal response is improved to an extremely slim deviation of 2.4%. Also a new class-AB rail-to-rail output stage is designed, targeting at high drive capability down to 33Omega resistive load, high power transfer efficiency and linearity. A modified measurement circuitry for fully differential opamps is introduced as well.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122701228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reconfigurable Switched-Capacitor ΔΣ Modulator Topology Design 可重构开关电容器ΔΣ调制器拓扑设计
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283865
Ying Wei, Pengbo Sun, A. Doboli
{"title":"Reconfigurable Switched-Capacitor ΔΣ Modulator Topology Design","authors":"Ying Wei, Pengbo Sun, A. Doboli","doi":"10.1109/SOCC.2006.283865","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283865","url":null,"abstract":"In this paper, a methodology for designing reconfigurable discrete-time DeltaSigma modulator topologies is proposed. Topologies are generated from a set of all possible topologies expressed by a generic topology, and optimized for minimizing the complexity of the topologies, maximizing the topology robustness with respect to circuit nonidealities, and minimizing total power consumption. The paper presents a case study for designing topologies for a three-mode reconfigurable DeltaSigma modulator. The paper also offers a reconfigurable topology implementation on a programmable system-on-chip (PSoC) device.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124271092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CMOS Low-Noise, Low-Dropout Regulator for Transceiver SOC Supply Management 用于收发器SOC电源管理的CMOS低噪声、低差稳压器
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283832
W. Oh, B. Bakkaloglu, B. Aravind, Siew Kuok Hoon
{"title":"A CMOS Low-Noise, Low-Dropout Regulator for Transceiver SOC Supply Management","authors":"W. Oh, B. Bakkaloglu, B. Aravind, Siew Kuok Hoon","doi":"10.1109/SOCC.2006.283832","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283832","url":null,"abstract":"Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is introduced. A secondary amplifier with supply ripple subtraction stage is used for PSR improvement. With the proposed techniques, less than 180 nV/radicHz output noise spectral density and 50 dB of PSR is measured at 10 kHz frequency. With chopping frequencies up to 1MHz, the regulator achieves 5 mV/25 mA load regulation at 100 muA quiescent current. The LN-LDO is designed and fabricated on a 0.25mum, digital CMOS process with five level metal occupying 0.54 mm2.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124684637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling 基于数据/位行解耦的高读取稳定性和低泄漏SRAM单元
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283862
Zhiyu Liu, V. Kursun
{"title":"High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling","authors":"Zhiyu Liu, V. Kursun","doi":"10.1109/SOCC.2006.283862","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283862","url":null,"abstract":"Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct coupling of data storage nodes to the bit lines during a read operation. Lowering of supply and threshold voltages leads to a significant degradation in SRAM cell stability with the scaling of CMOS technology. The SRAM cell stability is further degraded due to the process parameter variations in deeply scaled CMOS technologies. In addition to the data stability issues, the increasing leakage energy consumption of on-chip caches is another growing concern. In this paper, a new nine transistor (9T) SRAM cell with enhanced read stability and reduced leakage power consumption is proposed.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124676628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression 基于代码压缩的指令总线串扰节能编码
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283879
B. Vaidyanathan, Yuan Xie
{"title":"Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression","authors":"B. Vaidyanathan, Yuan Xie","doi":"10.1109/SOCC.2006.283879","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283879","url":null,"abstract":"Code compression techniques have been proposed to mitigate the problem of limited memory resources in embedded systems. As technology scales, reducing on-chip bus energy consumption is becoming important for embedded system designers. In this paper, we propose a crosstalk-aware energy-efficient code compression scheme, which can reduce inter-wire coupling transition induced instruction bus energy consumption, without sacrificing compression ratio. The experimental results show that the bus power consumption due to inter-wire coupling transition alone is reduced by 42-68% and the total bus power consumption is reduced by 55-71% for TMS320C6x benchmarks.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130268031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
eXtreme Energy Conservation for Mobile Communications 移动通信的极致节能
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283877
C. Chun
{"title":"eXtreme Energy Conservation for Mobile Communications","authors":"C. Chun","doi":"10.1109/SOCC.2006.283877","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283877","url":null,"abstract":"Rich multimedia content and processing-intensive applications are quickly moving from PCs to mobile communications devices, putting a tremendous strain on battery life and potentially creating a performance/stamina gap for users. Freescale's eXtreme energy conservation (XEC) technology addresses this gap with a holistic approach to power management, aligning low-level device and design techniques with system-level approaches to create a comprehensive solution to the power problem.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128999778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Mimo Receiver SOC for CDMA Applications 用于CDMA应用的Mimo接收器SOC
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283897
Tongtong Chen, Zhengtao Yu, Yuantao Peng, Yanbing Zhang, H. Dai, Xun Liu
{"title":"A Mimo Receiver SOC for CDMA Applications","authors":"Tongtong Chen, Zhengtao Yu, Yuantao Peng, Yanbing Zhang, H. Dai, Xun Liu","doi":"10.1109/SOCC.2006.283897","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283897","url":null,"abstract":"In this paper, we present a systems-on-chip (SoC) design for the 3G code division multiple access (CDMA) receiver using the multiple-input multiple-output (MIMO) technique. Our chip integrates the entire digital signal processing part of the receiver. Furthermore, the proposed design can be reconfigured in real-time to handle different modulation schemes based on the signal-to-noise ratio, resulting in the highly efficient use of spectrum and energy. Designed using a 0.18 mum standard cell library, our chip has a core area of 20 mm2 and achieves a maximal throughput of 5 Mbps in simulation with 610 mW power dissipation.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"652 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116094119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Crosstalk-aware Energy Reduction in NoC Communication Fabrics NoC通信结构中串扰感知的能耗降低
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283886
P. Pande, Haibo Zhu, A. Ganguly, C. Grecu
{"title":"Crosstalk-aware Energy Reduction in NoC Communication Fabrics","authors":"P. Pande, Haibo Zhu, A. Ganguly, C. Grecu","doi":"10.1109/SOCC.2006.283886","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283886","url":null,"abstract":"Interconnect fabrics of multi-core systems - on-chip are confronted with increased crosstalk effects and energy dissipation. Crosstalk avoidance coding (CAC) is a promising way to reduce the coupling capacitance of the interconnect wires. We propose a method to address both crosstalk and energy dissipation in networks-on-chip (NoC) by modifying the structure of the data packets and reducing the number of coding-decoding operations. Our results show that by incorporating crosstalk avoidance coding (CAC) schemes in the NoC data stream it is possible to save a significant amount of energy while communicating between multiple IP cores.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125782479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Energy-Aware MPEG-4 Single Profile in HW-SW Multi-Platform Implementation HW-SW多平台实现中的能量感知MPEG-4单一配置文件
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283833
A. Portero, G. Talavera, M. Montón, Borja Martínez, Marc Moreno, F. Catthoor, J. Carrabina
{"title":"Energy-Aware MPEG-4 Single Profile in HW-SW Multi-Platform Implementation","authors":"A. Portero, G. Talavera, M. Montón, Borja Martínez, Marc Moreno, F. Catthoor, J. Carrabina","doi":"10.1109/SOCC.2006.283833","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283833","url":null,"abstract":"Developers of next generation Multi-Processor Systems-on-a-chip (MPSoC) silicon platforms used in multimedia mobile devices should design efficient systems for diverse execution time vs. energy consumption trade-offs for a given quality of service. By exploiting Dynamic Voltage and Frequency Scaling (DVFS) techniques we can obtain singular computational/power trades offs points and thus design energy efficient platforms. This paper presents a high level methodology to acquire an optimal set of working points for an MPEG-4 Single Profile (SP) Video encoder implementation. The flow starts from a MPEG-4 encoder described in C++ language which is translated to a SystemC hard/soft description which will be analyzed and further mapped into different platforms. Refined code is migrated to four different processor architectures: a processor research framework (CRISP-Trimaran), a soft core processor with specific functional units implemented on an Altera FPGA, an ASIC and a classic DSP.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134162624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System 数据通信系统循环注入时钟乘法器中的定时抖动减小技术
2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI: 10.1109/SOCC.2006.283864
Q. Du, J. Zhuang, T. Kwasniewski
{"title":"A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System","authors":"Q. Du, J. Zhuang, T. Kwasniewski","doi":"10.1109/SOCC.2006.283864","DOIUrl":"https://doi.org/10.1109/SOCC.2006.283864","url":null,"abstract":"This paper presents a jitter reduction technique utilized in a cyclic injection DLL clock generator to improve the output timing jitter performance for data communication systems. An auxiliary loop with a period error detector finely tunes the VCDL delay value to minimize the period variations. Programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 0.9 GHz to 2.9 GHz. The circuit is implemented in 0.18 mum CMOS technology and a significant cycle- to-cycle timing jitter reduction from 21 ps to 2.5 ps at 2.9 GHz is obtained from the measured results when the jitter reduction technique is enabled. The measured phase noise is -119.6 dBc/Hz at 100 kHz offset with the carrier frequency of 2.795 GHz.","PeriodicalId":345714,"journal":{"name":"2006 IEEE International SOC Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123884425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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