Z. Wang, M. Berroth, U. Nowotny, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider
{"title":"7.5 Gb/s Monolithically Integrated Clock Recovery using PLL and 0.3 μM Gate Length Quantum Well HEMTs","authors":"Z. Wang, M. Berroth, U. Nowotny, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider","doi":"10.18419/OPUS-8204","DOIUrl":"https://doi.org/10.18419/OPUS-8204","url":null,"abstract":"A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO has been introduced. The VCO has a centre oscillating frequency of about 7.5 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at the bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at the supply voltage of -5 V.","PeriodicalId":344528,"journal":{"name":"ESSCIRC '93: Nineteenth European Solid-State Circuits Conference","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}