2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR)最新文献_第4页

ComCell: Exploring flexible and symmetrical architecture for data center networks ComCell:探索数据中心网络的灵活对称架构

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2016-06-14 DOI: 10.1109/HPSR.2016.7525632

Deshun Li, Yanming Shen

引用次数: 0

A spectrum allocation method based on distributed control plane in elastic optical networks 弹性光网络中基于分布式控制平面的频谱分配方法

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2016-06-14 DOI: 10.1109/HPSR.2016.7525652

Yuya Hiraiwa, K. Baba

引用次数: 0

High speed multipath computation algorithm for optical circuit and packet switching integrated network 用于光电路和分组交换综合网络的高速多径计算算法

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2016-06-14 DOI: 10.1109/HPSR.2016.7525649

Masaki Osako, Y. Tanigawa, Y. Hirota, H. Tode

引用次数: 0

TWIN as a future-proof optical transport technology for next generation metro networks TWIN是下一代城域网的一种面向未来的光传输技术

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2016-06-14 DOI: 10.1109/HPSR.2016.7525644

A. Triki, Ion Popescu, A. Gravey, X. Cao, T. Tsuritani, P. Gravey

{"title":"TWIN as a future-proof optical transport technology for next generation metro networks","authors":"A. Triki, Ion Popescu, A. Gravey, X. Cao, T. Tsuritani, P. Gravey","doi":"10.1109/HPSR.2016.7525644","DOIUrl":"https://doi.org/10.1109/HPSR.2016.7525644","url":null,"abstract":"The continuous growth of the traffic at a rapid pace raises challenges related to the efficient use of resources and saving of energy in the transport network. The new traffic pattern is characterized by faster growth of metro traffic compared with core, due in part to video content replication. In this paper, we compare the resource requirements of three different transport technologies (optical packet switching, opaque circuit switching and transparent circuit switching) within two architecture scenarios (the current hub-and-spoke architecture and the next generation distributed architecture). The comparison study takes into consideration the predicted traffic growth from 2014 to 2019 and the potential traffic decentralization due to content replication. For the optical packet switching, we focus on Time-domain Wavelength Interleaved Network (TWIN) solution which achieves passive switching at the intermediate nodes thanks to the precomputed optical packet emission schedule. Results show that TWIN outperforms the other transport technologies in terms of number of transmitters and receivers with a high ability to cope with scalability issues.","PeriodicalId":342055,"journal":{"name":"2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123930014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Combining forward error correction and network coding in bufferless networks: A case study for optical packet switching 无缓冲网络中前向纠错与网络编码的结合:以光分组交换为例

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2016-06-14 DOI: 10.1109/HPSR.2016.7525640

G. Biczók, Yanling Chen, Katina Kralevska, H. Øverby

{"title":"Combining forward error correction and network coding in bufferless networks: A case study for optical packet switching","authors":"G. Biczók, Yanling Chen, Katina Kralevska, H. Øverby","doi":"10.1109/HPSR.2016.7525640","DOIUrl":"https://doi.org/10.1109/HPSR.2016.7525640","url":null,"abstract":"Bufferless network operation is favorable in many application domains such as industrial networks, on-chip networks and optical packet switching (OPS). The main challenge with zero buffers is the avoidance or handling of contention; indeed, many domain-specific contention resolution techniques have been proposed in the literature. In this paper, we propose a generic combined forward error correction (FEC) and network coding (NC) scheme, which mitigates the negative impact of contentions at the network layer. Specifically, we present a case study for OPS utilizing FEC at the ingress node and NC at an intermediary optical packet switch to reduce packet loss due to contention. Our analysis shows that if used in a smart way, our mechanism can reduce decoding error and packet loss with multiple orders of magnitude while adhering to buffering limitations and meeting delay requirements. We believe that such a combined coding scheme has the potential to be utilized both in OPS (data center and core networks) and other networks where (near-)zero buffers are required.","PeriodicalId":342055,"journal":{"name":"2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133770184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

P4GPU: Acceleration of programmable data plane using a CPU-GPU heterogeneous architecture P4GPU:使用CPU-GPU异构架构加速可编程数据平面

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2016-06-14 DOI: 10.1109/HPSR.2016.7525662

Peilong Li, Yan Luo

{"title":"P4GPU: Acceleration of programmable data plane using a CPU-GPU heterogeneous architecture","authors":"Peilong Li, Yan Luo","doi":"10.1109/HPSR.2016.7525662","DOIUrl":"https://doi.org/10.1109/HPSR.2016.7525662","url":null,"abstract":"The programmability of the network data plane has become one of the most desirable features within the context of software defined networks, with P4 serving as a domain-specific language for defining data plane processing. In this work, we are motivated to address the challenges of mapping a P4 defined data plane to a heterogeneous programmable hardware architecture consisting of both a CPU and a GPU, which includes a salient parallel SIMD architecture for processing network flows. We first design a toolset that can be used to map a P4 program onto the proposed architecture. We then optimize the GPU kernel designs for “match-action” primitives and present latency-hiding techniques to reduce the overheads of CPU/GPU communication. In addition, load balancing is investigated to maximize the utilization of CPU and GPU resources. Our toolset and optimizations allow a P4 program to render promising performance on the given heterogeneous architecture. Specifically, the experimental results collected on our prototype systems show that the automatically configured GPU kernels achieve scalable lookup and classification speeds with 420 million IP lookups per second, and more than 60 million classifications per second (for 4K firewall rules).","PeriodicalId":342055,"journal":{"name":"2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR)","volume":"12 19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127270112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

IP prefix hijack detection using BGP connectivity monitoring 使用BGP连通性监控IP前缀劫持检测

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2016-06-14 DOI: 10.1109/HPSR.2016.7525636

Hussain Alshamrani, B. Ghita

{"title":"IP prefix hijack detection using BGP connectivity monitoring","authors":"Hussain Alshamrani, B. Ghita","doi":"10.1109/HPSR.2016.7525636","DOIUrl":"https://doi.org/10.1109/HPSR.2016.7525636","url":null,"abstract":"In spite of significant on-going research, the Border gateway protocol (BGP) still encompasses conceptual vulnerability issues regarding impersonating the ownership of IP prefixes for ASes (Autonomous Systems). In this context, a number of research studies focused on securing BGP through historical-based and statistical-based behavioural models. This paper suggests a novel method based on tracking the connectivity of suspicious ASes, which are received from a program tracing IP prefix hijacking signature. The paper uses Full Cross-Validation test to investigate the accuracy of the invented method and studies the similarity and differences between malicious and benign observations before they are classified. Classification might not be the appropriate technique to deal with IP prefix hijack detection on its own; therefore we propose to combine the two methods (signature and classification-based) in order to cover the limitations of both techniques. From a processing perspective, the outputs from signature-based method are used as inputs for the classification-based. The main features are extracted from the ASpath attributes of potentially suspicious ASes. The features are considered a mixture of the behavioural characteristics of connectivity among routers. The best five supervised classifiers were used in the previous researches and go with the characteristics of dataset will be used in this paper to evaluate the detection method. Under different learning algorithms, Random Forest and J48 classifiers, the detection method is able to detect the hijacks with 81% accuracy.","PeriodicalId":342055,"journal":{"name":"2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123617022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Cost-efficient data backup for data center networks against ε-time early warning disaster 针对ε时间预警灾害的数据中心网络经济高效的数据备份

2016 IEEE 17th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2015-12-27 DOI: 10.1109/HPSR.2016.7525634

Lisheng Ma, Xiaohong Jiang, Bin Wu, T. Taleb, A. Pattavina, N. Shiratori

引用次数: 6