Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)最新文献

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Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning 基于自动时空电路划分的混合功率仿真技术的维特比译码器IP的快速准确功率验证
M. Chinosi, R. Zafalon, C. Guardiani
{"title":"Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning","authors":"M. Chinosi, R. Zafalon, C. Guardiani","doi":"10.1109/CICC.1999.777238","DOIUrl":"https://doi.org/10.1109/CICC.1999.777238","url":null,"abstract":"A new technique for spatial and temporal partitioning of a logic circuit simulation, based on the nodes activity computed at an higher level of abstraction is presented in this paper. Only those components who are sensitized by a given input vector are added to the detailed netlist for electric simulation. The methodology is suitable for parallel implementation on a multi-processor environment and allows one to arbitrarily switch between fast and detailed level of abstraction during the simulation run. This technique has been successfully applied, among the others, to the verification of a fully synthesizable IP designed to achieve the optimal implementation of a Viterbi decoder over a wide range of parametric circuit configurations. The experimental results obtained on a further significant set of benchmarks show that it is possible to obtain a considerable reduction in both CPU time and memory allocation and yet keeping the high accuracy which is peculiar of the electric simulation. In addition, the proposed technique easily fits in the existing industrial verification flows.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131661715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS pipelined ADC employing dither to improve linearity CMOS流水线ADC采用抖动来提高线性度
H. S. Fetterman, D. G. Martin, D. Rich
{"title":"CMOS pipelined ADC employing dither to improve linearity","authors":"H. S. Fetterman, D. G. Martin, D. Rich","doi":"10.1109/CICC.1999.777253","DOIUrl":"https://doi.org/10.1109/CICC.1999.777253","url":null,"abstract":"This paper presents a new method for applying linearity improving dither to a pipelined ADC employing digital error correction. This dither energy remains internal to the converter, only causing correctable errors in the internal uncorrected digital data stream. Unlike adding dither to the input signal, this new dither method does not consume signal bandwidth or dynamic range. Spurious free dynamic range improvements of 15 dB have been realized.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128982263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Intermodulation analysis of mixer circuits based on frequency domain relaxation method 基于频域松弛法的混频器电路互调分析
A. Ushida, Y. Yamagami, Y. Nishio, Masayuki Takahashi, Kimihiro Ogawa
{"title":"Intermodulation analysis of mixer circuits based on frequency domain relaxation method","authors":"A. Ushida, Y. Yamagami, Y. Nishio, Masayuki Takahashi, Kimihiro Ogawa","doi":"10.1109/CICC.1999.777233","DOIUrl":"https://doi.org/10.1109/CICC.1999.777233","url":null,"abstract":"There are many communication circuits driven by multi-tone signals such as modulators and mixers. If the output frequency components are largely different to each other, the brute force numerical method will take an enormous computation time to calculate the steady-state responses, because the total period becomes very long. In this paper, we show a SPICE oriented algorithm based on the frequency domain relaxation method which can be efficiently applied to relatively large scale ICs.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126617823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3.25 Gb/s injection locked CMOS clock recovery cell 3.25 Gb/s注入锁定CMOS时钟恢复单元
T. Gabara
{"title":"A 3.25 Gb/s injection locked CMOS clock recovery cell","authors":"T. Gabara","doi":"10.1109/CICC.1999.777335","DOIUrl":"https://doi.org/10.1109/CICC.1999.777335","url":null,"abstract":"A clock signal embedded in a NRZ (Non Return to Zero) 2/sup 31/-1 pseudo-random data stream is used to injection lock a slave CMOS LC tank circuit. The slave oscillator in turn generates a clock signal responsive to this stimulus and is used to capture the data. A measured Bit Error Rate (BER) of less than 2E-15 at 3 Gb/s is achieved using conventional 0.25 /spl mu/m CMOS and dissipating less than 50 mW. Differential clock recovery can be performed with as little as four active devices.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"225 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120979899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An ultralow power single-chip CMOS 900 MHz receiver for wireless paging 一种用于无线寻呼的超低功耗单芯片CMOS 900 MHz接收器
H. Darabi, A. Abidi
{"title":"An ultralow power single-chip CMOS 900 MHz receiver for wireless paging","authors":"H. Darabi, A. Abidi","doi":"10.1109/CICC.1999.777276","DOIUrl":"https://doi.org/10.1109/CICC.1999.777276","url":null,"abstract":"Describes a low power CMOS wireless receiver. Its performance is summarised and its performance compared with integrated bipolar paging receivers. Some parameters have been normalized to enable meaningful comparison. This receiver's sensitivity is comparable, and its linearity is superior. Its power consumption is close to the lowest. Yet the final implementation bears little resemblance to the bipolar predecessors, and has been arrived at by uniquely CMOS considerations.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130849423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
RF transmitter architectures and circuits 射频发射机结构和电路
Behzad Razavi
{"title":"RF transmitter architectures and circuits","authors":"Behzad Razavi","doi":"10.1109/CICC.1999.777273","DOIUrl":"https://doi.org/10.1109/CICC.1999.777273","url":null,"abstract":"This paper describes the design of RF transmitters for wireless applications. Following a review of constant- and variable-envelope modulation, general issues regarding the baseband/RF interface and the power amplifier/antenna interface are introduced. Various transmitter architectures are then presented and the design of upconversion mixers and power amplifiers is studied. Examples of state of the art are also described.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"66 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116258686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 120
Wave pipelining YADDs-a feasibility study 波浪管道yads -可行性研究
A. Mukherjee, M. Marek-Sadowska, S. Long
{"title":"Wave pipelining YADDs-a feasibility study","authors":"A. Mukherjee, M. Marek-Sadowska, S. Long","doi":"10.1109/CICC.1999.777343","DOIUrl":"https://doi.org/10.1109/CICC.1999.777343","url":null,"abstract":"In this paper we study circuit structures obtained from direct mapping to pass transistor logic (PTL) of Yet Another Decision Diagrams (YADDs). These structures have almost equal delays along all the paths which makes wave pipelining possible. We discuss the details of a complete design, clocking and layout. In 0.5 /spl mu/m CMOS technology, YADDs can be clocked at a fixed rate of 715 MHz for any function. Our experimental results suggest that 4 times increase of speed over standard cell design is on the average possible for the price of similar area increase.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130893518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells 一种62.5- 250mhz多相延迟锁定环路,使用带有三重控制延迟单元的复制延迟线
Yongsam Moon, J. Choi, Kyeongho Lee, D. Jeong, Min-Kyu Kim
{"title":"A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells","authors":"Yongsam Moon, J. Choi, Kyeongho Lee, D. Jeong, Min-Kyu Kim","doi":"10.1109/CICC.1999.777295","DOIUrl":"https://doi.org/10.1109/CICC.1999.777295","url":null,"abstract":"This paper describes a low-jitter multi-phase delay-locked loop (DLL) with a wide operating range of 62.5-250 MHz. A replica delay line attached to the core DLL enables it to fully utilize the frequency range of its voltage-controlled delay line. The DLL incorporates dynamic phase detectors and triply controlled delay cells with duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip is fabricated using a 0.35 /spl mu/m CMOS process. The measured jitter is suppressed to be less than 44 ps peak-to-peak over the operating frequency range in a noisy environment with other digital circuits activated on the same chip.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128507774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hard disk drive read channels: technology and trends 硬盘驱动器读通道:技术和趋势
Hemat Thapar, Sang-Soo Lee, C. Conroy, R. Contreras, A. Yeung, Jenn-Gang Chern, T. Pan, S. Shih
{"title":"Hard disk drive read channels: technology and trends","authors":"Hemat Thapar, Sang-Soo Lee, C. Conroy, R. Contreras, A. Yeung, Jenn-Gang Chern, T. Pan, S. Shih","doi":"10.1109/CICC.1999.777297","DOIUrl":"https://doi.org/10.1109/CICC.1999.777297","url":null,"abstract":"Advances in read channel technology over the past 8 years have contributed approximately 50% to the areal density growth in magnetic hard disk drive (HDD) systems. This paper provides an overview of HDD read channel technology and trends. Dominant channel impairments are discussed along with signal processing methods to mitigate their effects. Equalization and coding techniques, capable of achieving higher areal densities, are reviewed. Finally, circuit design challenges in meeting the emerging data rate requirement of 1 Gb/s in read channel products are discussed.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122145593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Beyond 1 GHz [microprocessor design] 1 GHz以上[微处理器设计]
H. P. Hofstee, K. Nowka
{"title":"Beyond 1 GHz [microprocessor design]","authors":"H. P. Hofstee, K. Nowka","doi":"10.1109/CICC.1999.777243","DOIUrl":"https://doi.org/10.1109/CICC.1999.777243","url":null,"abstract":"This presentation reports on ongoing work at the IBM Austin Research Laboratory following the development of the 1 GHz microprocessor prototype. We discuss how to realize larger microprocessor designs without sacrificing cycle time, and we discuss some of the challenges we face in achieving frequencies that are significantly higher than 1 GHz.","PeriodicalId":340693,"journal":{"name":"Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123123434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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