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[1988] Proceedings. International Conference on Systolic Arrays最新文献

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Bit-level systolic arrays for IIR filtering 用于IIR滤波的位级收缩数组
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18102
S. C. Knowles, Roger Francis Woods, J. McWhirter, J. McCanny
{"title":"Bit-level systolic arrays for IIR filtering","authors":"S. C. Knowles, Roger Francis Woods, J. McWhirter, J. McCanny","doi":"10.1109/ARRAYS.1988.18102","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18102","url":null,"abstract":"A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115354897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Homogeneous multicomputer type DSP system NOVI for parallel signal processing 同构多机型DSP系统NOVI用于并行信号处理
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18097
N. Ohta, T. Fujii, Y. Kanayama, S. Ono
{"title":"Homogeneous multicomputer type DSP system NOVI for parallel signal processing","authors":"N. Ohta, T. Fujii, Y. Kanayama, S. Ono","doi":"10.1109/ARRAYS.1988.18097","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18097","url":null,"abstract":"The architecture and performance of a multicomputer-type digital signal processing (DSP) system are discussed. The DSP system, called NOVI, has been created to examine methods for organizing parallel DSP systems and developing parallel programs for a wide range of digital signal processing applications. NOVI presently consists of 36 processing elements (PEs), each using an Inmos Transputer as a CPU. Its parallel-program-development assistant (PDA) system facilitates powerful debugging functions to observe all PE state without any interference to parallel program execution. A parallel-program-development technique using the PDA is discussed. A load-balancing technique on a multicomputer-type DSP is also discussed, focusing on low-bit-rate motion-picture coding. The balancing technique is based on interframe prediction and layered large-grain data flow. The expected performance of the NOVI system is discussed.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127245268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scheduling a system of affine recurrence equations onto a systolic array 将一个仿射递推方程组调度到一个收缩阵列上
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18077
Y. Yaacoby, P. Cappello
{"title":"Scheduling a system of affine recurrence equations onto a systolic array","authors":"Y. Yaacoby, P. Cappello","doi":"10.1109/ARRAYS.1988.18077","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18077","url":null,"abstract":"Most work on the problem of scheduling computations on a systolic array is restricted to systems of uniform recurrence equations. This restriction is relaxed to include systems of affine recurrence equations. In this broader class, a sufficient condition is given for the system to be computable. Necessary and sufficient conditions are given for the existence of an affine schedule, along with a procedure that constructs the schedule vector when one exists.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130137046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
The derivation of regular synchronous circuits 规则同步电路的推导
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18071
W. Luk, G. Jones
{"title":"The derivation of regular synchronous circuits","authors":"W. Luk, G. Jones","doi":"10.1109/ARRAYS.1988.18071","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18071","url":null,"abstract":"An approach to derive parameterized representations of regular synchronous circuits from their specification is presented. The derivation of designs consists of two steps: rewriting the specification in terms of predefined structures to obtain a draft architecture, and optimizing that architecture by successive correctness-preserving transformations using algebraic theorems. These steps can be repeated to obtain, at a lower level of abstraction, architectures that still satisfy the original specification. A number of word-level and bit-level rank evaluator designs are developed to illustrate the techniques describes.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121704307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Systolic FFT algorithms on Boolean cube networks 布尔立方体网络的收缩FFT算法
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18056
L. Johnson, Chat-Tin Ho, M. Jacquemin, A. Ruttenberg
{"title":"Systolic FFT algorithms on Boolean cube networks","authors":"L. Johnson, Chat-Tin Ho, M. Jacquemin, A. Ruttenberg","doi":"10.1109/ARRAYS.1988.18056","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18056","url":null,"abstract":"A description is given of a systolic Cooley-Tukey fast Fourier transform algorithm for Boolean n-cubes with a substantial amount of storage per cube node. In mapping a Cooley-Tukey type FFT to such a network, the main concerns are effective use of the high connectivity/bandwidth of the Boolean n-cube, the computational resources, the storage bandwidth, if there is a storage hierarchy, and the pipelines should the arithmetic units have such a feature. Another important consideration in a multiprocessor, distributed storage architecture is the allocation and access to coefficients, if they are precomputed. FFT algorithms are described that use both the storage bandwidth and the communication system optimally and require storage of P+nN coefficients for a transform on P>or=N data elements. A complex-to-complex FFT on 16 million points is predicted to require about 1.5 s on a Connection Machine model CM-2.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126295678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Architecture of SIPS, a real time image processing system 实时图像处理系统SIPS的体系结构
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18099
A. Hasebe, J. Yonemitsu, R. Kato, N. Ito, H. Fujita
{"title":"Architecture of SIPS, a real time image processing system","authors":"A. Hasebe, J. Yonemitsu, R. Kato, N. Ito, H. Fujita","doi":"10.1109/ARRAYS.1988.18099","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18099","url":null,"abstract":"A real-time image processing system called SIPS (Sight Information Processing System) has been designed and constructed. SIPS realizes a high-speed performance of 2.7 Giga operations/s through parallel and distributed processing of its 82 independently controlled processors. SIPS provides both real-time processing of color video images and a high degree of flexibility. SIPS became operational in 1985 and has been used for research on video image processing such as low-level vision processing and image coding. The architectures and possible applications of SIPS are presented.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114787802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An efficient systolic array for MVDR beamforming 一种用于MVDR波束形成的高效收缩阵列
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18039
J. McWhirter, T. Shepherd
{"title":"An efficient systolic array for MVDR beamforming","authors":"J. McWhirter, T. Shepherd","doi":"10.1109/ARRAYS.1988.18039","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18039","url":null,"abstract":"An efficient systolic array for computing the minimum variance distortionless response (MVDR) from an adaptive antennas array is described. The MVDR beamforming problem amounts to minimizing, in a least-squares sense, the combined output from an antenna array subject of K independent linear equality constraints each of which corresponds to a chosen 'look direction'. The array is fully pipelined and based on numerically stable algorithm that requires O(p/sup 2/+Kp) arithmetic operations per sample time, where p is the number of antenna elements.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121321173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The use of linear arrays for image processing 使用线性阵列进行图像处理
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18059
T. J. Fountain
{"title":"The use of linear arrays for image processing","authors":"T. J. Fountain","doi":"10.1109/ARRAYS.1988.18059","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18059","url":null,"abstract":"The problem of deciding upon an architecture that is suitable for a broad spectrum of image-processing applications is presently unsolved, at least partly because of the intrinsic difficulty of the processing tasks involved. The author considers the claims of one candidate, the linear array, by examining its generic characteristics and surveying a number of current systems. The author also considers a number of the technical factors involved in the design of such systems and proposes a novel implementation that appears to offer several advantages.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"20 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114124222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
HIFI: a functional design system for VLSI processing arrays HIFI:用于VLSI处理阵列的功能设计系统
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18081
J. Annevelink, P. Dewilde
{"title":"HIFI: a functional design system for VLSI processing arrays","authors":"J. Annevelink, P. Dewilde","doi":"10.1109/ARRAYS.1988.18081","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18081","url":null,"abstract":"An overview is given of a design system called HIFI, for hierarchical interactive integration. It is a design system for VLSI that allows hierarchical refinement of pipelined signal (equivalently data) flowgraphs, until an architecture is obtained that can be realized in hardware. It is based on an extended definition of a signal flowgraph in which a CSP-like communication model is utilized on functional nodes. The model is chosen so that any deterministic system can be described by it and so that it can be decomposed or reassembled hierarchically in a consistent manner. Type-decomposition of edges is allowed as well. A prototype of the system has been implemented using Smalltalk. A number of examples have been worked out, of which one, a system for transitive closure, is presented.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134327387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A block algorithm for the algebraic path problem and its execution on a systolic array 代数路径问题的块算法及其在收缩数组上的执行
[1988] Proceedings. International Conference on Systolic Arrays Pub Date : 1988-05-25 DOI: 10.1109/ARRAYS.1988.18067
F. J. Nuñez, M. Valero
{"title":"A block algorithm for the algebraic path problem and its execution on a systolic array","authors":"F. J. Nuñez, M. Valero","doi":"10.1109/ARRAYS.1988.18067","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18067","url":null,"abstract":"The solution of the algebraic path problem (APP) for arbitrarily sized graphs by a fixed-size systolic array processor (SAP) is addressed. The APP is decomposed into two subproblems, and SAP is designed for each one. Both SAPs combined produce a highly implementable versatile SAP. The proposed SAP has p*p processing elements (PEs) solving the APP of an N-vertex graph in N/sup 3//p/sup 2/+N/sup 2//p+3p-2 cycles. With slight modifications in the operations performed by the PEs, the problem is optimally solved in N/sup 3//p/sup 2/+3p-2 cycles.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"25 3-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129777885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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