Proceedings of International Conference on Application Specific Array Processors (ASAP '93)最新文献

Systolic evaluation of functions: Digit-level algorithm and realization 收缩函数的评估:数字级算法与实现

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397171

S. Johansen

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引用次数: 1

An optimal algo-tech-cuit for the knapsack problem 背包问题的最优算法技术电路

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397174

R. Andonov, S. Rajopadhye

引用次数: 12

Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design 节点合并:高效VLSI阵列设计中位相关图的转换

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397165

Bongjin Jung, W. Burleson

{"title":"Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design","authors":"Bongjin Jung, W. Burleson","doi":"10.1109/ASAP.1993.397165","DOIUrl":"https://doi.org/10.1109/ASAP.1993.397165","url":null,"abstract":"The authors present a transformation technique, called node merging, on bit-level dependence graphs to systematically explore tradeoffs between area and various system performances, such as clock period, pipelining period, block pipelining period, computation time, and dynamic power dissipation to obtain optimal VLSI array processors for bit-level regular algorithms. By merging several DG nodes into one node, multi-bit level array processors can be designed using formal regular array synthesis methods thereby significantly reducing the number of pipelining registers required compared to bit-pipelined array processors. In general, delay paths within a node in bit-level dependence graphs are unbalanced, and the clock period is determined by the critical path delay. By merging nodes along noncritical paths, the authors improve computation time as well as VLSI area with a relatively small increase in clock period and pipelining period. They also expand the complexity of node functions enough to apply a meaningful logic optimization or performance enhancement using well-known logic synthesis tools such as SIS for even further improvement. Since the transformation results in a new DG, it can be easily combined with conventional VLSI array synthesis techniques for efficient bit-level array processor design. Therefore, the method provides an efficient way to explore a significantly broader design space in VLSI array processor design.<<ETX>>","PeriodicalId":337209,"journal":{"name":"Proceedings of International Conference on Application Specific Array Processors (ASAP '93)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126898236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mapping Monte Carlo-Metropolis algorithm onto a double ring architecture 将蒙特卡罗-大都会算法映射到双环结构上

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397143

G. Danese, I. Lotto, D. Dotti, D. Lanterna, F. Leporati, R. Lombardi, S. Romano

引用次数: 0

Reconfigurable hardware for molecular biology computing systems 用于分子生物学计算系统的可重构硬件

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397141

E. Lemoine

引用次数: 5

Time-optimal visibility-related algorithms on meshes with multiple broadcasting 多广播网格上的时间最优可视性相关算法

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397147

D. Bhagavathi, V. Bokka, H. Gurla, S. Olariu, J. Schwing, I. Stojmenovic, Jingyuan Zhang

引用次数: 6

Efficient architecture of a programmable block matching processor 一种高效的可编程块匹配处理器结构

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397175

L. Vos, M. Schöbinger

引用次数: 8

A CAD tool for electromagnetic simulation on the associative string processor 基于关联串处理器的电磁仿真CAD工具

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397177

Darren Patrick Rodohan, S. Saunders

引用次数: 2

An efficient algorithm for image-template product on SIMD mesh connected computers SIMD网格连接计算机上图像模板生成的一种高效算法

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397149

Hongchi Shi, G. Ritter, Joseph N. Wilson

引用次数: 8

Digit systolic algorithms for fine-grain architectures 细粒度结构的数字收缩算法

Proceedings of International Conference on Application Specific Array Processors (ASAP '93) Pub Date : 1993-10-25 DOI: 10.1109/ASAP.1993.397167

Chetana N. Keltcher, R. Owens, M. J. Irwin

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引用次数: 9