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Preemption-aware planning on big-data systems 大数据系统的抢占意识规划
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851187
Marco Rabozzi, Matteo Mazzucchelli, R. Cordone, Giovanni Matteo Fumarola, M. Santambrogio
{"title":"Preemption-aware planning on big-data systems","authors":"Marco Rabozzi, Matteo Mazzucchelli, R. Cordone, Giovanni Matteo Fumarola, M. Santambrogio","doi":"10.1145/2851141.2851187","DOIUrl":"https://doi.org/10.1145/2851141.2851187","url":null,"abstract":"Recent developments in Big Data frameworks are moving towards reservation based approaches as a mean to manage the increasingly complex mix of computations, whereas preemption techniques are employed to meet strict jobs deadlines. Within this work we propose and evaluate a new planning algorithm in the context of reservation based scheduling. Our approach is able to achieve high cluster utilization while minimizing the need for preemption that causes system overheads and planning mispredictions.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116803814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Articulation points guided redundancy elimination for betweenness centrality 铰接点引导冗余消除之间的中心
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851154
Lei Wang, Fan Yang, Liangji Zhuang, Huimin Cui, Fang Lv, Xiaobing Feng
{"title":"Articulation points guided redundancy elimination for betweenness centrality","authors":"Lei Wang, Fan Yang, Liangji Zhuang, Huimin Cui, Fang Lv, Xiaobing Feng","doi":"10.1145/2851141.2851154","DOIUrl":"https://doi.org/10.1145/2851141.2851154","url":null,"abstract":"Betweenness centrality (BC) is an important metrics in graph analysis which indicates critical vertices in large-scale networks based on shortest path enumeration. Typically, a BC algorithm constructs a shortest-path DAG for each vertex to calculate its BC score. However, for emerging real-world graphs, even the state-of-the-art BC algorithm will introduce a number of redundancies, as suggested by the existence of articulation points. Articulation points imply some common sub-DAGs in the DAGs for different vertices, but existing algorithms do not leverage such information and miss the optimization opportunity. We propose a redundancy elimination approach, which identifies the common sub-DAGs shared between the DAGs for different vertices. Our approach leverages the articulation points and reuses the results of the common sub-DAGs in calculating the BC scores, which eliminates redundant computations. We implemented the approach as an algorithm with two-level parallelism and evaluated it on a multicore platform. Compared to the state-of-the-art implementation using shared memory, our approach achieves an average speedup of 4.6x across a variety of real-world graphs, with the traversal rates up to 45 ~ 2400 MTEPS (Millions of Traversed Edges per Second).","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123760495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Production-guided concurrency debugging 生产指导的并发调试
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851149
Nuno Machado, Brandon Lucia, L. Rodrigues
{"title":"Production-guided concurrency debugging","authors":"Nuno Machado, Brandon Lucia, L. Rodrigues","doi":"10.1145/2851141.2851149","DOIUrl":"https://doi.org/10.1145/2851141.2851149","url":null,"abstract":"Concurrency bugs that stem from schedule-dependent branches are hard to understand and debug, because their root causes imply not only different event orderings, but also changes in the control-flow between failing and non-failing executions. We present Cortex: a system that helps exposing and understanding concurrency bugs that result from schedule-dependent branches, without relying on information from failing executions. Cortex preemptively exposes failing executions by perturbing the order of events and control-flow behavior in non-failing schedules from production runs of a program. By leveraging this information from production runs, Cortex synthesizes executions to guide the search for failing schedules. Production-guided search helps cope with the large execution search space by targeting failing executions that are similar to observed non-failing executions. Evaluation on popular benchmarks shows that Cortex is able to expose failing schedules with only a few perturbations to non-failing executions, and takes a practical amount of time.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117245992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
GPU multisplit GPU multisplit
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851169
Saman Ashkiani, Andrew A. Davidson, Ulrich Meyer, John D. Owens
{"title":"GPU multisplit","authors":"Saman Ashkiani, Andrew A. Davidson, Ulrich Meyer, John D. Owens","doi":"10.1145/2851141.2851169","DOIUrl":"https://doi.org/10.1145/2851141.2851169","url":null,"abstract":"Multisplit is a broadly useful parallel primitive that permutes its input data into contiguous buckets or bins, where the function that categorizes an element into a bucket is provided by the programmer. Due to the lack of an efficient multisplit on GPUs, programmers often choose to implement multisplit with a sort. However, sort does more work than necessary to implement multisplit, and is thus inefficient. In this work, we provide a parallel model and multiple implementations for the multisplit problem. Our principal focus is multisplit for a small number of buckets. In our implementations, we exploit the computational hierarchy of the GPU to perform most of the work locally, with minimal usage of global operations. We also use warp-synchronous programming models to avoid branch divergence and reduce memory usage, as well as hierarchical reordering of input elements to achieve better coalescing of global memory accesses. On an NVIDIA K40c GPU, for key-only (key-value) multisplit, we demonstrate a 3.0-6.7x (4.4-8.0x) speedup over radix sort, and achieve a peak throughput of 10.0 G keys/s.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117248031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High performance model based image reconstruction 基于高性能模型的图像重建
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851163
Xiao Wang, Amit Sabne, S. Kisner, A. Raghunathan, C. Bouman, S. Midkiff
{"title":"High performance model based image reconstruction","authors":"Xiao Wang, Amit Sabne, S. Kisner, A. Raghunathan, C. Bouman, S. Midkiff","doi":"10.1145/2851141.2851163","DOIUrl":"https://doi.org/10.1145/2851141.2851163","url":null,"abstract":"Computed Tomography (CT) Image Reconstruction is an important technique used in a wide range of applications, ranging from explosive detection, medical imaging to scientific imaging. Among available reconstruction methods, Model Based Iterative Reconstruction (MBIR) produces higher quality images and allows for the use of more general CT scanner geometries than is possible with more commonly used methods. The high computational cost of MBIR, however, often makes it impractical in applications for which it would otherwise be ideal. This paper describes a new MBIR implementation that significantly reduces the computational cost of MBIR while retaining its benefits. It describes a novel organization of the scanner data into super-voxels (SV) that, combined with a super-voxel buffer (SVB), dramatically increase locality and prefetching, enable parallelism across SVs and lead to an average speedup of 187 on 20 cores.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126432119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
An interval constrained memory allocator for the Givy GAS runtime 用于Givy GAS运行时的间隔约束内存分配器
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851195
François Gindraud, F. Rastello, Albert Cohen, François Broquedis
{"title":"An interval constrained memory allocator for the Givy GAS runtime","authors":"François Gindraud, F. Rastello, Albert Cohen, François Broquedis","doi":"10.1145/2851141.2851195","DOIUrl":"https://doi.org/10.1145/2851141.2851195","url":null,"abstract":"The shared memory model helps parallel programming productivity, but it also has a high hardware cost and imposes scalability constraints. Ultimately, higher performance will use distributed memories, which scales better but requires programmers to manually transfer data between local memories, which is a complex task. Distributed memories are also more energy efficient than shared memories, and are used in a family of embedded computing solutions called multi processor system on chip (MPSoC).","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126520444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On designing NUMA-aware concurrency control for scalable transactional memory 可扩展事务内存的numa感知并发控制设计
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851189
Mohamed Mohamedin, R. Palmieri, Sebastiano Peluso, B. Ravindran
{"title":"On designing NUMA-aware concurrency control for scalable transactional memory","authors":"Mohamed Mohamedin, R. Palmieri, Sebastiano Peluso, B. Ravindran","doi":"10.1145/2851141.2851189","DOIUrl":"https://doi.org/10.1145/2851141.2851189","url":null,"abstract":"NUMA architectures posed the challenge of rethinking parallel applications due to the non-homogeneity introduced by their design, and their real benefits are limited to the characteristics of the particular workload. We name as partitionable transactional workloads such workloads that may be able to exploit the distributed nature of NUMA, such as transactional workloads where data and accesses can be easily partitioned among the so called NUMA zones. However, in case those workloads require the synchronization on shared data, we have to face the issue of exploiting the NUMA architecture also in the concurrency control for their transactions. Therefore in this paper we present a NUMA-aware concurrency control for transactional memory that we designed for promoting scalability in scenarios where both the transactional workload is prone to scale, and the characteristics of the underlying memory model are inherently non-uniform, such as NUMA architectures.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131400366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Generic messages: capability-based shared memory parallelism for event-loop systems 通用消息:事件循环系统的基于功能的共享内存并行性
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851184
Luca Salucci, Daniele Bonetta, Stefan Marr, Walter Binder
{"title":"Generic messages: capability-based shared memory parallelism for event-loop systems","authors":"Luca Salucci, Daniele Bonetta, Stefan Marr, Walter Binder","doi":"10.1145/2851141.2851184","DOIUrl":"https://doi.org/10.1145/2851141.2851184","url":null,"abstract":"Systems based on event-loops have been popularized by Node.JS, and are becoming a key technology in the domain of cloud computing. Despite their popularity, such systems support only share-nothing parallelism via message passing between parallel entities usually called workers. In this paper, we introduce a novel parallel programming abstraction called Generic Messages (GEMs), which enables shared-memory parallelism for share-nothing event-based systems. A key characteristic of GEMs is that they enable workers to share state by specifying how the state can be accessed once it is shared. We call this aspect of the GEMs model capability-based parallelism.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115185447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Declarative coordination of graph-based parallel programs 基于图的并行程序的声明性协调
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851153
Flávio Cruz, Ricardo Rocha, S. Goldstein
{"title":"Declarative coordination of graph-based parallel programs","authors":"Flávio Cruz, Ricardo Rocha, S. Goldstein","doi":"10.1145/2851141.2851153","DOIUrl":"https://doi.org/10.1145/2851141.2851153","url":null,"abstract":"Declarative programming has been hailed as a promising approach to parallel programming since it makes it easier to reason about programs while hiding the implementation details of parallelism from the programmer. However, its advantage is also its disadvantage as it leaves the programmer with no straightforward way to optimize programs for performance. In this paper, we introduce Coordinated Linear Meld (CLM), a concurrent forward-chaining linear logic programming language, with a declarative way to coordinate the execution of parallel programs allowing the programmer to specify arbitrary scheduling and data partitioning policies. Our approach allows the programmer to write graph-based declarative programs and then optionally to use coordination to fine-tune parallel performance. In this paper we specify the set of coordination facts, discuss their implementation in a parallel virtual machine, and show---through example---how they can be used to optimize parallel execution. We compare the performance of CLM programs against the original uncoordinated Linear Meld and several other frameworks.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117288253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Scalable adaptive NUMA-aware lock: combining local locking and remote locking for efficient concurrency 可伸缩的自适应numa感知锁:结合本地锁定和远程锁定，实现高效的并发性
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Pub Date : 2016-02-27 DOI: 10.1145/2851141.2851176
Mingzhe Zhang, F. Lau, Cho-Li Wang, Luwei Cheng, Haibo Chen
{"title":"Scalable adaptive NUMA-aware lock: combining local locking and remote locking for efficient concurrency","authors":"Mingzhe Zhang, F. Lau, Cho-Li Wang, Luwei Cheng, Haibo Chen","doi":"10.1145/2851141.2851176","DOIUrl":"https://doi.org/10.1145/2851141.2851176","url":null,"abstract":"Scalable locking is a key building block for scalable multi-threaded software. Its performance is especially critical in multi-socket, multi-core machines with non-uniform memory access (NUMA). Previous schemes such as local locking and remote locking only perform well under a certain level of contention, and often require non-trivial tuning for a particular configuration. Besides, for large NUMA systems, because of unmanaged lock server's nomination, current distance-first NUMA policies cannot perform satisfactorily. In this work, we propose SANL, a locking scheme that can deliver high performance under various contention levels by adaptively switching between the local and the remote lock scheme. Furthermore, we introduce a new NUMA policy for the remote lock that jointly considers node distances and server utilization when choosing lock servers. A comparison with seven representative locking schemes shows that SANL outperforms the others in most contention situations. In one group test, SANL is 3.7 times faster than RCL lock and 17 times faster than POSIX mutex.","PeriodicalId":336502,"journal":{"name":"Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129021340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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