Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools最新文献

Embedded software: how to make it efficient? 嵌入式软件:如何使其高效?

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115370

P. Marwedel

引用次数: 11

Integration of instruction set simulators into SystemC high level models 将指令集模拟器集成到SystemC高级模型中

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115360

Ilia Oussorov, W. Raab, J. Hachmann, A. Kravtsov

引用次数: 9

A hybrid evolutionary algorithm for Multi-FPGA systems design 一种多fpga系统设计的混合进化算法

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115352

J. Hidalgo, J. Lanchares, Aitor Ibarra, R. Hermida

引用次数: 8

Bit-level allocation of multiple-precision specifications 多精度规格的位级分配

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115396

M. Molina, J. Mendias, R. Hermida

引用次数: 0

An asynchronous victim cache 异步受害者缓存

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115345

D. Hormdee, J. Garside, S. Furber

{"title":"An asynchronous victim cache","authors":"D. Hormdee, J. Garside, S. Furber","doi":"10.1109/DSD.2002.1115345","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115345","url":null,"abstract":"Memory bandwidth is a limiting factor with many modem microprocessors and it is usual to include a cache to reduce the amount of memory traffic. Of the two commonly used cache write-policies, the copy-back approach is better than the write-through approach in this respect. The performance of both approaches can be further aided by the inclusion of a small buffer in the path of outgoing writes to the main memory, especially if this buffer is capable of forwarding its contents back into the main cache if they are needed again before they are emptied from the buffer This is what is known as a victim cache. For an asynchronous microprocessor it is logical that the cache system should be asynchronous as well; since a large degree of the flexibility of an asynchronous microprocessor would be lost if it were to use a standard synchronous memory interface. However implementing a forwarding mechanism in an asynchronous system is more difficult because the data to be forwarded is flowing in a manner unsynchronised to the process which requires it. This paper presents an architecture for a victim cache to resolve forwarding in a totally asynchronous environment. The resultant structure forms a key part of an asynchronous copy-back cache system for the Amulet3, a third generation asynchronous implementation of the ARM processor.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124309801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Speeding up elliptic cryptosystems using a new signed binary representation for integers 使用新的带符号二进制整数表示法加快椭圆密码系统速度

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115395

R. Katti

引用次数: 10

Reconfigurable hardware implementation of Montgomery modular multiplication and parallel binary exponentiation 蒙哥马利模乘法和并行二进制幂的可重构硬件实现

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115373

N. Nedjah, L. M. Mourelle

引用次数: 25

Simplifying instruction issue logic in superscalar processors 简化超标量处理器中的指令发布逻辑

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115388

Toshinori Sato, I. Arita

{"title":"Simplifying instruction issue logic in superscalar processors","authors":"Toshinori Sato, I. Arita","doi":"10.1109/DSD.2002.1115388","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115388","url":null,"abstract":"Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is difficult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant determiners of processor cycle time. The instruction window is critical because it is realized using content addressable memory (CAM). In general, RAMs are faster in access time and lower in power dissipation than CAMs. Therefore, it is desirable that the CAM instruction window is replaced by the RAM instruction window. This paper proposes such an instruction window, named the explicit data forwarding instruction window. The principle behind our proposal is to make result forwarding explicit. It is possible to dynamically construct explicit relationships between instructions, since it is expected that each execution result is forwarded to a limited number of dependent instructions. Simulation results show that the explicit data forwarding instruction window achieves a level of performance comparable to that of the conventional instruction window, while also providing benefit in terms of shorter cycle time.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130089207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Reachability analysis for formal verification of SystemC SystemC正式验证的可达性分析

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115387

R. Drechsler, Daniel Große

引用次数: 43

An evaluation of an FPGA run-time support system FPGA运行时支持系统的评估

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI: 10.1109/DSD.2002.1115382

P. Green, M. Vakondios, M. Edwards

引用次数: 3