Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.最新文献

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Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems MIMO OFDM系统中MMSE检测器结构的复杂性分析
M. Myllyla, J.-H. Hintikka, Joseph R. Cavallaro, M. Juntti, M. Limingoja, A. Byman
{"title":"Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems","authors":"M. Myllyla, J.-H. Hintikka, Joseph R. Cavallaro, M. Juntti, M. Limingoja, A. Byman","doi":"10.1109/ACSSC.2005.1599705","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1599705","url":null,"abstract":"In this paper, a field programmable gate array (FPGA) implementation of a linear minimum mean square error (LMMSE) detector is considered for MIMO-OFDM systems. Two square root free algorithms based on QR decomposition (QRD) are introduced for the implementation of LMMSE detector. Both algorithms are based on QRD via Givens rotations, namely coordinate rotation digital computer (CORDIC) and squared Givens rotation (SGR) algorithms. Linear and triangular shaped array architectures are considered to exploit (he parallelism in the computations. An FPGA hardware implementation is presented and computational complexity of each implementation is evaluated and compared","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115140408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Analysis of Decision-Feedback Based Broadband OFDM Systems 基于决策反馈的宽带OFDM系统分析
A. de Baynast, A. Sabharwal, B. Aazhang
{"title":"Analysis of Decision-Feedback Based Broadband OFDM Systems","authors":"A. de Baynast, A. Sabharwal, B. Aazhang","doi":"10.1109/ACSSC.2005.1599840","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1599840","url":null,"abstract":"In wireless communications, about 25% of the bandwidth is dedicated to training symbols for channel estimation. By using a semi-blind approach, the training sequence length can be reduced while improving performance. The principle is as follows: the detected symbols (hard decision) are fed back to the channel estimator in order to re-estimate the channel more accurately. However, semi-blind approach can significantly deteriorate the performance if the bit error rate is high. In this paper, we propose to determine analytically the minimum signal to noise ratio (SNR) from which a semi-blind method starts to outperform a training sequence based only system","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm 基于QRD-RLS算法的矩阵反演FPGA实现
M. Karkooti, Joseph R. Cavallaro, C. Dick
{"title":"FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm","authors":"M. Karkooti, Joseph R. Cavallaro, C. Dick","doi":"10.1109/ACSSC.2005.1600043","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1600043","url":null,"abstract":"This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 × 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125026913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 159
Modelling Heterogeneous DSP-FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment 基于异构DSP-FPGA的系统划分建模及其对菠菜仿真环境的扩展
M. Brogioli, Joseph R. Cavallaro
{"title":"Modelling Heterogeneous DSP-FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment","authors":"M. Brogioli, Joseph R. Cavallaro","doi":"10.1109/ACSSC.2005.1600044","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1600044","url":null,"abstract":"In this paper we present system-on-a-chip exten- sions to the Spinach simulation environment for rapidly prototyp- ing heterogeneous DSP/FPGA based architectures, specifically in the embedded domain. This infrastructure has been successfully used to model systems varying from multiprocessor gigabit ethernet controllers to Texas Instruments C6x series DSP based systems with tightly coupled FPGA based coprocessors for com- putational offloading. As an illustrative example of this toolsets functionality, we investigate workload partitioning in heteroge- neous DSP/FPGA based embedded environments. Specifically, we focus on computational offloading of matrix multiplication kernels across DSP/FPGA based embedded architectures. I. INTRODUCTION","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128988840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Cross-Layer Approach to Cognitive MAC for Spectrum Agility 面向频谱敏捷性的认知MAC跨层方法
Qing Zhao, L. Tong, A. Swami
{"title":"A Cross-Layer Approach to Cognitive MAC for Spectrum Agility","authors":"Qing Zhao, L. Tong, A. Swami","doi":"10.1109/ACSSC.2005.1599732","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1599732","url":null,"abstract":"Opportunistic spectrum access aims to exploit the instantaneous spectrum availability using sophisticated signal processing and networking techniques. Cognitive MAC that enables instantaneous detection and efficient utilization of spectrum opportunities is one of the key components of opportunistic spectrum access. In this paper, we pursue a cross-layer approach that integrates opportunity assessment and opportunity allocation for optimal spectrum utilization. We develop optimal cognitive MAC protocols for multihop ad hoc networks","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"53 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130842999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Symbol Synchronisation Implementation for Low-Power RF Communication in Wireless Sensor Networks 无线传感器网络中低功耗射频通信的符号同步实现
N. MacEwen, L. Crockett, E. Pfann, R. Stewart
{"title":"Symbol Synchronisation Implementation for Low-Power RF Communication in Wireless Sensor Networks","authors":"N. MacEwen, L. Crockett, E. Pfann, R. Stewart","doi":"10.1109/ACSSC.2005.1599787","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1599787","url":null,"abstract":"Speckled computing is a novel vision of a wireless sensor network consisting of small nodes which can sense, compute and network wirelessly. The nodes individually have limited power and processing resources, but together forms a powerful processing system. Electrical power resources at such a volume are severely restricted, and as such design decisions are made with low-power as the first priority. This work examines the use of Manchester encoding in the digital transceiver to reduce the complexity of symbol synchronisation. A Manchester decoder has been implemented which has the useful property of being tolerant to oscillator inaccuracies, allowing a cheap and low-power clock source to be employed. A realistic implementation of the decoder using rectangular pulse-shaping and an oversampling ratio of 8 allows an on-chip oscillator tolerance of more than 11%","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124435389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimized Message Passing Schedules for LDPC Decoding LDPC解码的优化消息传递调度
P. Radosavljevic, A. de Baynast, Joseph R. Cavallaro
{"title":"Optimized Message Passing Schedules for LDPC Decoding","authors":"P. Radosavljevic, A. de Baynast, Joseph R. Cavallaro","doi":"10.1109/ACSSC.2005.1599818","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1599818","url":null,"abstract":"The major drawback of the LDPC codes versus the turbo-codes is their comparative low convergence speed: 25-30 iterations vs. 8-10 iterations for turbo-codes. Recently, Hocevar showed by simulations that the convergence rate of the LDPC decoder can be accelerated by exploiting a `turbo-scheduling' applied on the bit-node messages (rows of the parity check matrix). In this paper, we show analytically that the convergence rate for this type of scheduling is about two times increased for most of the regular LDPC codes. Second we prove that `turbo-scheduling' applied on the rows of the parity check matrix is identical belief propagation algorithm as standard message passing algorithm. Furthermore, we propose two new message passing schedules: 1) a turbo-scheduling is applied on the check-node messages (columns of the parity check matrix); and 2) a hybrid version of both previous schedules where the turbo-effect is applied on both check-nodes and bit-nodes. Frame error rate simulations validate the effectiveness of the proposed schedules","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133397648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
Self-Orthogonalizing Overlap-Save GSC 自正交重叠-节省GSC
C. L. Koh, S. Weiss, J. M. Peterson, S. Bharitkar
{"title":"Self-Orthogonalizing Overlap-Save GSC","authors":"C. L. Koh, S. Weiss, J. M. Peterson, S. Bharitkar","doi":"10.1109/ACSSC.2005.1600057","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1600057","url":null,"abstract":"This paper discusses a computationally inexpensive and fast converging approach to broadband beamforming. Exemplarily utilising the generalised sidelobe canceller (GSC), accurate low-cost implementations in the DFT domain based on overlap-save techniques have been previously suggested, which however suffer from slow convergence when used in combination with the least mean squares algorithm. To overcome this limitation, the beamformer proposed here exploits decorrelation of the input signal within the overlap-save architecture. By inclusion of a self-orthogonalizing component into the adaptive algorithm, the eigenvalue spread of the covariance matrix of the input signal is reduced, thereby increasing the adaptation rate. Simulation results indicate that the convergence speed of the proposed beamformer is comparable to a time domain realisation, albeit at a much reduced cost.","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Variable-Rate Universal Slepian-Wolf Coding with Feedback 带反馈的可变速率通用睡狼编码
S. Sarvotham, D. Baron, Richard Baraniuk
{"title":"Variable-Rate Universal Slepian-Wolf Coding with Feedback","authors":"S. Sarvotham, D. Baron, Richard Baraniuk","doi":"10.1109/ACSSC.2005.1599690","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1599690","url":null,"abstract":"Traditional Slepian-Wolf coding assumes known statistics and relies on asymptotically long sequences. However, in practice the statistics are unknown, and the input sequences are of finite length. In this finite regime, we must allow a non-zero probability of codeword error isin and also pay a penalty by adding redundant bits in the encoding process. In this paper, we develop a universal scheme for Slepian-Wolf coding that allows encoding at variable rates close to the Slepian-Wolf limit. We illustrate our scheme in a setup where we encode a uniform Bernoulli source sequence and the second sequence, which is correlated to the first via a binary symmetric correlation channel, is available as side information at the decoder. This specific setup is easily extended to more general settings. For length n source sequences and a fixed isin, we show that the redundancy of our scheme is O(radicnPhi-1(isin)) bits over the Slepian-Wolf limit. The prior art for Slepian-Wolf coding with known statistics shows that the redundancy is Omega(radicnPhi-1(isin)). Therefore, we infer that for Slepian-Wolf coding, the penalty needed to accommodate universality is thetas(radicnPhi-1(isin))","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130184573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Simple Seed Architectures for Reciprocal and Square Root Reciprocal 倒数和平方根倒数的简单种子结构
M. Ercegovac, J. Muller, A. Tisserand
{"title":"Simple Seed Architectures for Reciprocal and Square Root Reciprocal","authors":"M. Ercegovac, J. Muller, A. Tisserand","doi":"10.1109/ACSSC.2005.1599944","DOIUrl":"https://doi.org/10.1109/ACSSC.2005.1599944","url":null,"abstract":"This paper presents a simple hardware architecture for computing the seed values for reciprocal and square root reciprocal. These seeds are used in the intitialization of floating-point division and square root software iterations. The proposed solution is based on polynomial approximation with specific coefficients and a table lookup.","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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