2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献

Asynchronous sub-threshold ultra-low power processor 异步亚阈值超低功耗处理器

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347592

R. Diamant, R. Ginosar, C. Sotiriou

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引用次数: 6

Response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platform 考虑异构集群平台上DVFS延迟的硬实时系统响应时间可调度性分析

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347580

E. Valentin, Mário Salvatierra, Rosiane de Freitas, R. Barreto

引用次数: 6

Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse 通过位下降和位重用，在近似sram中降低优于电压的缩放能量

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347598

F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto

{"title":"Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse","authors":"F. Frustaci, D. Blaauw, D. Sylvester, M. Alioto","doi":"10.1109/PATMOS.2015.7347598","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347598","url":null,"abstract":"This paper explores the effectiveness of different knobs to dynamically trade energy consumption with output quality in approximate SRAMs for error-tolerant applications (such as video). Leveraging the different impact of errors on quality at most significant bit (MSB) and least significant bit (LSB) positions, energy savings higher than those provided by simple voltage scaling are enabled. Firstly, a comparison of two techniques, dual-VDD and LSB dropping, is carried out showing that the latter is preferable thanks to its intrinsic simplicity and more pronounced energy savings. Secondly, a selective Error Correction Code (ECC) technique which reuses the LSBs as check bits to protect MSBs is investigated. Measurements on a 28nm CMOS 32kb SRAM show that bit dropping and bit reuse achieve an energy reduction of up to 33% and 28%, compared to simple voltage scaling at iso-quality. When combined together, the two techniques achieve a better energy saving (40%) and a supply voltage reduction of about 100mV at iso-quality. Finally, guidelines to select the energy-optimal combination of the two techniques are provided for a given quality target.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Energy management via PI control for data parallel applications with throughput constraints 通过PI控制对具有吞吐量限制的数据并行应用程序进行能源管理

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347588

A. Molnos, W. Lombardi, D. Puschini, Julien Mottin, S. Lesecq, A. Tonda

引用次数: 1

VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard 针对IEEE 802.22 WRAN标准的VLSI架构设计并实现了LDPC编码器

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347589

Nelson Alves Ferreira Neto, J. Oliveira, Wagner Oliveira, Joao Carlos Bittencourt

引用次数: 4

ABeeMap: A mapping algorithm based on multi-objective Artificial Bee Colony ABeeMap:一种基于多目标人工蜂群的映射算法

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347582

V. L. Souza, A. Silva-Filho, V. C. Wanderely

引用次数: 0

Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architecture Zipf流量分布在Facebook数据中心结构架构中的能源效率

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347601

L. Durbeck, J. Tront, N. Macias

引用次数: 11

Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency 将Pel抽取与部分失真消除相结合提高SAD能量效率

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347604

Ismael Seidel, André Beims Bräscher, José Luís Almada Güntzel

{"title":"Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency","authors":"Ismael Seidel, André Beims Bräscher, José Luís Almada Güntzel","doi":"10.1109/PATMOS.2015.7347604","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347604","url":null,"abstract":"The most energy-hungry step of Video Coding (VC) is the Block Matching Algorithm (BMA), even when a simple similarity metric such as the Sum of Absolute Differences (SAD) is employed. Moreover, with the increasing resolutions supported by state-of-the-art VC standards (H.264/AVC, HEVC and VP9), the SAD must be as energy-efficient as possible to increase the battery lifetime in portable mobile devices. Two well-known techniques to decrease the number of operations in SAD calculation are Pel Decimation and Partial Distortion Elimination (PDE). The energy savings provided by the former are dictated by the chosen decimation ratio and comes with a cost in coding efficiency. For the latter, energy savings have no cost in coding efficiency but are dictated by the video content and search parameters. In this work we present two configurable SAD4×4 architectures: one designed to dynamically operate using one among four Pel Decimation ratios (1:1, 4:3, 2:1 or 4:1) and the other one able to use PDE in addition to Pel Decimation. We simulated Pel Decimation and PDE behavior during motion estimation using 22 video samples from the Common Test Conditions (CTC) encoded using 4 different quantization parameters (QPs). Thus, this simulation was performed over 5.82×1012 PDE SADs. The Pel Decimation impacts are shown in terms of Bjøntegaard Delta (BD)-Rate, ranging from 3.16% (1:1 ratio) up to 21.94% (4:1). In addition, we found that by using PDE solely (i.e., without Pel Decimation) one can reduce from 10 to 6.38 (in average) the number of required cycles to calculate one SAD. To show the improvements in terms of energy, we synthesized both presented architectures using a 45nm standard cell library. Finally, the use of PDE can improve energy efficiency more than Pel Decimation alone, without coding efficiency degradation.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121283865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Wideband dynamic voltage sensing mechanism for EH systems EH系统的宽带动态电压传感机制

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347605

K. Gao, Y. Xu, D. Shang, Fei Xia, A. Yakovlev

引用次数: 3

Energy-efficient Level Shifter topology 节能电平移位拓扑

2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2015-12-07 DOI: 10.1109/PATMOS.2015.7347600

Roger Caputo-Llanos, Diego V. S. Sousa, M. Terres, G. Bontorin, R. Reis, M. Johann

引用次数: 0