2009 International Conference on Reconfigurable Computing and FPGAs最新文献_第2页

Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations FPGA中的十进制加/减法器:高效的6输入LUT实现

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.29

M. Vazquez, G. Sutter, G. Bioul, J. Deschamps

引用次数: 19

Enhancing the Productivity of Radio Designers with RapidRadio 提高生产力的无线电设计师与RapidRadio

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.84

J. Surís, A. Recio, P. Athanas

引用次数: 4

FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition 用于字符识别的Izhikevich脉冲神经网络的FPGA实现

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.77

Kenneth L. Rice, M. Bhuiyan, T. Taha, Christopher N. Vutsinas, M. C. Smith

{"title":"FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition","authors":"Kenneth L. Rice, M. Bhuiyan, T. Taha, Christopher N. Vutsinas, M. C. Smith","doi":"10.1109/ReConFig.2009.77","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.77","url":null,"abstract":"There has been a strong push recently to examine biological scale simulations of neuromorphic algorithms to achieve stronger inference capabilities than current computing algorithms. The recent Izhikevich spiking neuron model is ideally suited for such large scale cortical simulations due to its efficiency and biological accuracy. In this paper we explore the feasibility of using FPGAs for large scale simulations of the Izhikevich model. We developed a modularized processing element to evaluate a large number of Izhikevich spiking neurons in a pipelined manner. This approach allows for easy scalability of the model to larger FPGAs. We utilized a character recognition algorithm based on the Izhikevich model for this study and scaled up the algorithm to use over 9000 neurons. The FPGA implementation of the algorithm on a Xilinx Virtex 4 provided a speedup of approximately 8.5 times an equivalent software implementation on a 2.2 GHz AMD Opteron core. Our results indicate that FPGAs are suitable for large scale cortical simulations utilizing the Izhikevich spiking neuron model.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116329447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 96

Effects of Simplistic Online Synthesis for AMIDAR Processors 简化在线合成对AMIDAR处理器的影响

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.21

Stefan Döbrich, C. Hochberger

引用次数: 4

PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems PCIREX: TMR动态可重构系统的快速原型平台

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.33

A. Astarloa, Jesús Lázaro, U. Bidarte, A. Zuloaga, J. Jiménez

引用次数: 4

Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go 基于三重线的围棋播放-蒙特卡洛围棋加速器

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.75

Kenichi Koizumi, M. Inaba, K. Hiraki, Y. Ishii, T. Miyoshi, Kazuki Yoshizoe

{"title":"Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go","authors":"Kenichi Koizumi, M. Inaba, K. Hiraki, Y. Ishii, T. Miyoshi, Kazuki Yoshizoe","doi":"10.1109/ReConFig.2009.75","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.75","url":null,"abstract":"After a computer named “Deep Blue” defeated the world chess champion Garry Kasparov in 1997, researchers studying computer board games focused their attention on the game “Go.” Go is known to be more difficult for computers to play than chess or shogi because (1) the search space for Go is much larger, (2) it is difficult to define an appropriate evaluation function of position, and (3) a position sometimes changes globally in just one move. Recently, a new method called Monte Carlo Go has been developed, which involves performing Monte Carlo simulations to evaluate a position. Monte Carlo Go increases the strength of the Computer-Go program. For Monte Carlo Go, the strength fully depends on the number of simulations. Several attempts were made to accelerate simulations, e.g., by the use of cluster systems and FPGAs. The cluster system yields good results, but it is a very expensive system. On the other hand, acceleration using an FPGA was not so easy because the usage of FPGA resources tends to be high. Previously, FPGA acceleration was feasible for smaller board such as a board with a 9 × 9 grid, while it was not feasible for the standard board with a 19 × 19 grid. In this paper, we propose triple line-based playout for Go (TLPG), a hardware algorithm for generating simulations using an FPGA. By reproducing global information redundantly, TLPG enables the generation of simulations only using local operations; this helps realize compact implementations of hardware logic, and thus, TLPG can handle both 9 × 9 and 19 × 19 grid Go boards. We implement TLPG on Xilinx Virtex-5 (XC5VFX70T-1FF1136) and evaluate it. TLPG can perform 40,649 playouts per second for a 9 × 9 grid Go board and 4,668 playouts per second for a 19 × 19 grid Go board.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116775266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time Runtime Temporal Partitioning Assembly减少FPGA重构时间

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.61

Abelardo Jara-Berrocal, A. Gordon-Ross

引用次数: 16

Fuzzy Control for Cyclist Robot Stability Using FPGAs 基于fpga的自行车机器人稳定性模糊控制

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.53

C. Castro, C. Llanos, Walter de Britto Vidal Filho, L. Coelho

{"title":"Fuzzy Control for Cyclist Robot Stability Using FPGAs","authors":"C. Castro, C. Llanos, Walter de Britto Vidal Filho, L. Coelho","doi":"10.1109/ReConFig.2009.53","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.53","url":null,"abstract":"This paper presents a fuzzy controller implementation in FPGA (Field Programmable Gate Array) for a robot that rides a bicycle using the well-known Acrobot model. The overall system presents a hardware/software codesign approach and it was achieved by means of a Microblaze FPGA embedded processor and a fuzzy controller, which was implemented directly in hardware. Both the microprocessor and the controller are connected via the Fast Simplex Link - FSL bus. The proposed design methodology involves firstly the fuzzy controller design in software for simulation and testing issues, taking into account the mathematical model of the plant. Afterwards, the controller was synthesized to the hardware description language VHDL using the Xfuzzy 2.0 tool. The fuzzy controller has 2 modules, each one producing a torque control variable. The first module receives both the position and angular speed of the first link of the Acrobot system whereas the second module receives the position and angular speed of the second link. The final torque variable is calculated in the Microblaze taking into account two gains. Each gain represents a priority that is applied to each fuzzy module. These gains were experimentally calculated through several simulation executed in the Matlab computational environment.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard 3GPP标准中Turbo码可配置交织/去交织器的设计与实现

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.16

Hector Borrayo-Sandoval, R. Parra-Michel, L. F. Gonzalez-Perez, Fernando Landeros Printzen, C. F. Uribe

引用次数: 12

FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier 带并行定点乘法器的十进制浮点精确标量积单元的FPGA实现

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.17

Malte Baesler, T. Teufel

引用次数: 16