{"title":"Scalable compositional reachability analysis of real-time concurrent systems","authors":"Farn Wang","doi":"10.1109/RTTAS.1996.509535","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509535","url":null,"abstract":"A description model for high level behavior of a real time concurrent system is presented. A verification algorithm is then devised to take advantage of interaction locality and symmetry and internal operation concealment in the model. A system called VERIFAST implements the algorithm. Experiments show that VERIFAST runs fast and exhibits time complexity linear to the size of concurrency in a benchmark.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116687501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"DRTSS: a simulation framework for complex real-time systems","authors":"M. Storch, J. Liu","doi":"10.1109/RTTAS.1996.509533","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509533","url":null,"abstract":"This paper describes a simulation framework called DRTSS, which allows its users to easily construct discrete-event simulators of complex, multi-paradigm, distributed real-time systems. Preliminary, high-level system designs can be entered into DRTSS to gain initial insight into the timing feasibility of the system. Later, detailed hierarchical designs can be evaluated and more detailed analysis can be undertaken. DRTSS is a member of the PERTS family of timing-oriented prototyping and verification tools [17]. It complements the PERTS schedulability analyzer tool by dealing with complex real-lime systems for which a priori schedulability analysis is difficult or impossible.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129515682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of wireless soft real-time protocols","authors":"M. Markowski, A. Sethi","doi":"10.1109/RTTAS.1996.509531","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509531","url":null,"abstract":"Communication between current military real-time systems and future interconnection of general purpose, embedded real-time systems will often require wireless communications. However, there has been little work undertaken to offer support for real-time applications on wireless networks. We present and evaluate three protocols; variations of two published protocols by Paterakis and Gallager as well as our new one, the Sliding Partition (SP) collision resolution algorithm (CRA). In a real-time setting, the modified Gallager CRA consistently performs worst of the three we consider. We observe that when the deadline range is small, the Sliding Partition CRA performs best. When the deadline range is large, however, the Paterakis CRA performs slightly better than the SP CRA. Both analytic and simulation results are obtained to study the maximum input traffic rates that can be sustained for various laxities, delay bounds, and message loss rates.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124619547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"EMERALDS: a microkernel for embedded real-time systems","authors":"K. M. Zuberi, K. Shin","doi":"10.1109/RTTAS.1996.509541","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509541","url":null,"abstract":"EMERALDS (Extensible Microkernel for Embedded Real Time Distributed Systems) is a real time microkernel designed for cost conscious small to medium size embedded systems. It not only offers standard OS services like multi threaded processes, real time scheduling, protected address spaces, message passing, semaphores, and timers, but does so in an efficient manner while keeping the kernel size to just tens of kilobytes. For efficiency, EMERALDS uses the novel approach of mapping the kernel into each user level address space, so even with full memory protection, system calls do not need context switches unless a user level server is involved. EMERALDS also provides the flexibility for users to add communication protocol stacks and device drivers as user level servers without modifying the kernel. We have completed a uniprocessor version of EMERALDS for the Motorola 68040 processor whose size is under 13 KBytes. Context switch takes under 12 /spl mu/s and system calls have overhead just 1.8 /spl mu/s more than that of simple subroutine calls.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127026576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Temporal analysis and object-oriented real-time software development: a case study with ROOM/ObjecTime","authors":"Daniel Gaudrau, P. Freedman","doi":"10.1109/RTTAS.1996.509528","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509528","url":null,"abstract":"New generation methodologies and CASE tools are making possible increasing \"automation\" by addressing software development in terms of executable models. We describe one such methodology, ROOM, along with its CASE tool, ObjecTime, for which systems are modelled in terms of hierarchically organised communicating objects whose behavior is defined in terms of finite state machines. In particular, we present the results of a Rate Monotonic Analysis inspired temporal analysis which makes evident some of the runtime limitations associated with ROOM semantics and the way in which the ROOM model is cast as an executable for the intended embedded platform.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129888646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Busquets-Mataix, J. J. Serrano, Rafael Ors Carot, P. Gil, A. Wellings
{"title":"Adding instruction cache effect to schedulability analysis of preemptive real-time systems","authors":"J. Busquets-Mataix, J. J. Serrano, Rafael Ors Carot, P. Gil, A. Wellings","doi":"10.1109/RTTAS.1996.509537","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509537","url":null,"abstract":"Cache memories are commonly avoided in real time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. The paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to both cache partitioning (increase of the cache predictability by assigning private cache partitions to tasks) and CRMA (Cached RMA: cache effect is incorporated in the utilization based rate monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outperforms CRMA, however the partitioning scheme may be better depending on the system configuration. The obtained results bound the applicability domain for each method for a variety of hardware and workload configurations. The results can be used as design guidelines.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134583709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Resource management for real-time communication: making theory meet practice","authors":"A. Mehra, Atri Indiresan, K. Shin","doi":"10.1109/RTTAS.1996.509530","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509530","url":null,"abstract":"This paper focuses on bridging the gap between theory and practice in the management of host CPU and link resources for real-time communication. Using our implementation of real-time channels, a paradigm for real-time communication in packet-switched networks, we illustrate the tradeoff between resource capacity and channel admissibility, which determines the number and type of real-time channels that can be accepted for service and the performance delivered to best-effort traffic. We demonstrate that this tradeoff is affected significantly by the choice of implementation paradigms and the grain at which CPU and link resources are multiplexed amongst active channels. To account for this effect we extend the admission control procedure for real-time channels originally proposed using idealized resource models. Our results show that practical considerations significantly reduce channel admissibility compared to idealized resource models. Further, the optimum choice of multiplexing grain depends on several factors such as resource preemption overheads, the relationship between CPU and link bandwidth, and the interaction between link bandwidth allocation and CPU bandwidth allocation.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114515576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CAISARTS: a tool for real-time scheduling assistance","authors":"M. Humphrey, J. Stankovic","doi":"10.1109/RTTAS.1996.509532","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509532","url":null,"abstract":"CAISARTS (Conceptual, Analytical, and Implementation Scheduling Advice for Real-Time Systems) is a rule-based system used by real-time application designers to obtain expert assistance for all aspects of the design related to scheduling: granularity of tasks, allocation of tasks, choice and analysis of scheduling paradigm, analysis of overheads of particular operating systems and scheduling paradigms, and code templates for tasks. The rule base is partitioned; subsets of the rule base can be selected for firing, thus enabling the user to ask CAISARTS for advice and analysis relevant for different phases of the design. In contrast to existing real-time tools, CAISARTS attempts to cover the entire design process related to scheduling without focusing on, for example, solely schedulability analysis. A unique feature of CAISARTS is that its rule base is extensible by the user-a graphical interface is used to add new rules as new real-time results are identified. Challenges in the design of the initial rule set include how to design and partition the rule base so that it can be both easily modifiable and readily usable by the user in choosing rules to fire; how to encode rules that are inherently contradictory; how to encode ambiguous knowledge; and how to make the rules both comprehensive and precise. The effectiveness of CAISARTS is shown through its use on a representative distributed real-time system scenario with end-to-end constraints.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126047749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of a hardware/software platform for real-time data-intensive applications in hazardous environments","authors":"J. Fernández-Conde, A. García-Martínez, Á. Viña","doi":"10.1109/RTTAS.1996.509520","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509520","url":null,"abstract":"In real-time data-intensive applications, the simultaneous achievement of the required performance and determinism is a difficult issue to address, mainly due to the time needed to perform I/O operations, which is more significant than the CPU processing time. Additional features need to be considered if these applications are intended to perform in hostile environments. In this paper, we address the implementation of a hardware/software platform designed to acquire, transfer, process and store massive amounts of information at sustained rates of several MBytes/sec, capable of supporting real-time applications with stringent throughput requirements under hazardous environmental conditions. A real-world system devoted to the inspection of nuclear power plants is presented as an illustrative example.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126254287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lo Ko, Christopher A. Healy, Emily Ratliff, R. Arnold, D. Whalley, M. Harmon
{"title":"Supporting the specification and analysis of timing constraints","authors":"Lo Ko, Christopher A. Healy, Emily Ratliff, R. Arnold, D. Whalley, M. Harmon","doi":"10.1109/RTTAS.1996.509534","DOIUrl":"https://doi.org/10.1109/RTTAS.1996.509534","url":null,"abstract":"Real-time programmers have to deal with the problem of relating timing constraints associated with source code to sequences of machine instructions. This paper describes an environment to assist users in the specification and analysis of timing constraints. A user is allowed specify timing constraints within the source code of a C program. A user interface for a timing analyzer was developed to depict whether these constraints were violated or met. In addition, the interface allows portions of programs to be quickly selected with the corresponding bounded times, source code lines, and machine instructions automatically displayed The result is a user-friendly environment that supports the user specification and analysis of timing constraints at a high (source code) level and retains the accuracy of low (machine code) level analysis.","PeriodicalId":324830,"journal":{"name":"Proceedings Real-Time Technology and Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126357794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}