PerformancePub Date : 1980-05-28DOI: 10.1145/800199
K. Sevcik, G. S. Graham, G. Nutt
{"title":"Proceedings of the 1980 international symposium on Computer performance modelling, measurement and evaluation","authors":"K. Sevcik, G. S. Graham, G. Nutt","doi":"10.1145/800199","DOIUrl":"https://doi.org/10.1145/800199","url":null,"abstract":"","PeriodicalId":32394,"journal":{"name":"Performance","volume":"25 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73542686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PerformancePub Date : 1980-05-28DOI: 10.1145/800199.806159
A. Kurinckx, G. Pujolle
{"title":"Overallocation in a virtual circuit computer network","authors":"A. Kurinckx, G. Pujolle","doi":"10.1145/800199.806159","DOIUrl":"https://doi.org/10.1145/800199.806159","url":null,"abstract":"In this paper, we study the end-to-end control through virtual circuits in a computer network built following the X.25 Recommendations. We develop a mathematical model to obtain the maximum overallocation of node buffers, in order for the probability of overflow not to exceed a given value.","PeriodicalId":32394,"journal":{"name":"Performance","volume":"61 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78868601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PerformancePub Date : 1980-05-28DOI: 10.1145/800199.806162
D. Grit, R. Page
{"title":"Performance of a multiprocessor for Applicative programs","authors":"D. Grit, R. Page","doi":"10.1145/800199.806162","DOIUrl":"https://doi.org/10.1145/800199.806162","url":null,"abstract":"Applicative programming Languages provide opportunities for parallel processing without requiring the programmer to be concerned with explicit synchronization of portions of the computation. We present a computational model of a multiprocessor which executes applicative programs, and we analyze the expected performance of the model via simulation. As the number of processors is doubled, elapsed execution time is nearly halved, until system bottlenecks occur. An alternative model is proposed which alleviates these bottlenecks. The basis of the second model is an interconnection switch which is characterized by log(n) access time and n log(n) cost.","PeriodicalId":32394,"journal":{"name":"Performance","volume":"16 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82701196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PerformancePub Date : 1980-05-28DOI: 10.1145/800199.806148
D. Bashioum
{"title":"Benchmarking interactive systems: Calibrating the model","authors":"D. Bashioum","doi":"10.1145/800199.806148","DOIUrl":"https://doi.org/10.1145/800199.806148","url":null,"abstract":"A methodology for benchmarking dedicated, interactive systems has been developed at The MITRE Corporation. This methodology uses a synthetic program model of the application which runs on the proposed hardware/operating system configurations and is driven by a statistically derived load. System performance is measured by analyzing the synthetic transaction response times. The methodology yields assurances to a buyer that the benchmarked system has at least an a priori defined amount of computer power available for applications-oriented software. This paper examines the methodology and the problems that were encountered and solutions which have been used in calibrating a benchmark model for a specific application. The benchmark was designed to model a large interactive information processing application on a procurement requiring loosely-coupled (no shared memory) multicomputer systems. The model consists of a set of interacting synthetic program cells, each composed of several abstractly defined components. The model is maintained in a very high level language that is automatically translated into a standard High Order Language (typically FORTRAN or COBOL) for delivery to the competing vendors. These delivered model cells contain automatically generated size and time filler code that “calibrate” the cells to consume the appropriate CPU time and memory space as defined by the abstract size units after accounting for each vendor's hardware and proposed system design.","PeriodicalId":32394,"journal":{"name":"Performance","volume":"96 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76864882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PerformancePub Date : 1980-05-28DOI: 10.1145/800199.806170
D. Potier, Ph. Leblanc
{"title":"Analysis of locking policies in database management systems","authors":"D. Potier, Ph. Leblanc","doi":"10.1145/800199.806170","DOIUrl":"https://doi.org/10.1145/800199.806170","url":null,"abstract":"Quantitative analysis of locking mechanisms and of their impact on the performance of transactionnal systems have yet received relatively little attention. Although numerous concurrency mechanisms have been proposed and implemented, there is an obvious lack of experimental as well as analytical studies of their behaviour and their influence on system performance. We present in this paper an analytical framework for the performance analysis of locking mechanisms in transactionnal systems based on hierarchical analytical modelling. Three levels of modelling are considered: at level 1, the different stages (lock request, execution, blocking) transactions of through during their life-time are described; the organization and operations of the CPU and I/O resources are analysed at level 2; transaction's behaviour during their lock request phase is analysed at modelling level 3. This hierarchical approach is applied to the analysis of a physical locking scheme involving a static lock acquisition policy. A simple probabilistic model of the transaction behaviour is used to derived the probability that a new transaction is granted the locks it requests given the number of transactions already active as a function of the granularity of the database. On the other hand, the multiprogramming effect due to the sharing of CPU and I/O resources by transactions is analysed using the standard queueing network approaches and the solution package QNAP. In a final step, the results on the blocking probabilities and the multiprogrammin effect are used as input of a global performance model of the transactionnal system. Markovian analysis is used to solve this model and to obtain the throughput of the system as a function of the data base granularity and other parameters. The results obtained provide a clear understanding of the various factors which determine the global performance, of their role and improtance. They also raise many new issues which can only be solved by further extensive experimental and analytical studies and show that two particular topics deserve special attention: the modelling of transaction behaviour and the modelling of locking overheads.","PeriodicalId":32394,"journal":{"name":"Performance","volume":"54 5-6","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1145/800199.806170","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72491585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PerformancePub Date : 1980-05-28DOI: 10.1145/800199.806160
R. Upton, S. Tripathi
{"title":"Analysis of design alternatives for a packet switched I/O system","authors":"R. Upton, S. Tripathi","doi":"10.1145/800199.806160","DOIUrl":"https://doi.org/10.1145/800199.806160","url":null,"abstract":"This paper describes an application of analytical modeling to the design and evaluation of a general purpose, packet-switched image processing system that will soon enter an implementation phase. A bottom-up modeling approach is used to evaluate such design issues as optimal packet size, optimal channel access method(s), and required number of processors and disks. Based on the characteristics of various hardware components and the predicted workload, specific design recommendations are made.","PeriodicalId":32394,"journal":{"name":"Performance","volume":"31 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73079346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PerformancePub Date : 1980-05-28DOI: 10.1145/800199.806167
S. Lam, A. Shankar
{"title":"Response time distributions for a multi-class queue with feedback","authors":"S. Lam, A. Shankar","doi":"10.1145/800199.806167","DOIUrl":"https://doi.org/10.1145/800199.806167","url":null,"abstract":"A single server queue with feedback and multiple customer classes is analyzed. Arrival processes are independent Poisson processes. Each round of service is exponentially distributed. After receiving a round of service, a customer may depart or rejoin the end of the queue for more service. The number of rounds of service required by a customer is a random variable with a general distribution. Our main contribution is characterization of response time distributions for the customer classes. Our results generalize in some respects previous analyses of processor-sharing models. They also represent initial efforts to understand response time behavior along paths with loops in local balanced queueing networks.","PeriodicalId":32394,"journal":{"name":"Performance","volume":"559 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73686985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PerformancePub Date : 1980-05-28DOI: 10.1145/800199.806161
E. Balkovich, C. Whitby-Strevens
{"title":"On the performance of decentralized software","authors":"E. Balkovich, C. Whitby-Strevens","doi":"10.1145/800199.806161","DOIUrl":"https://doi.org/10.1145/800199.806161","url":null,"abstract":"Distribution of computing to achieve goals such as enhanced reliability depend on the use of decentralized software. Decentralization typically replaces a sequential process by a system of small, concurrent processes that interact frequently. The implementation of processes and their interactions represents a cost incurred as a result of decentralization. Performance measurements are reported in this paper for decentralized software written in a programming language for distributed computer systems. These performance measurements confirm that low-cost implementations of concurrency are possible, but indicate that decentralized software makes heavy use of run-time functions managing concurrency. An initial model comparing the performance of a specific decentralized software structure to its centralized counterpart indicates that these implementation costs are generally offset by the performance improvements that are due to the parallelism inherent in the decentralized structure. The research facilities for continued study of decentralized software performance are described in the summary.","PeriodicalId":32394,"journal":{"name":"Performance","volume":"350 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1980-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79770995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}