2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV)最新文献

Towards Property Driven Hardware Security 走向财产驱动的硬件安全

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.12

Wei Hu, Alric Althoff, Armita Ardeshiricham, R. Kastner

{"title":"Towards Property Driven Hardware Security","authors":"Wei Hu, Alric Althoff, Armita Ardeshiricham, R. Kastner","doi":"10.1109/MTV.2016.12","DOIUrl":"https://doi.org/10.1109/MTV.2016.12","url":null,"abstract":"Secure hardware design is a challenging task due to the fact that security properties are difficult or impossible to model and subsequently verify using traditional hardware design tools. The \"state of the art\" for hardware design security relies heavily on functional verification, manual inspection, and code review to identify security vulnerabilities. This labor intensive process significantly reduces productivity while proving no guarantee that a security flaw will be identified. In this paper, we describe a property driven approach to hardware security, which allows automatic synthesis and verification of both qualitative and quantitative security properties. We address hardware security by enforcing information flow and statistical security properties. By incorporating a new security property specification language, such security properties can be specified, translated and verified using hardware design tools. We present design examples to demonstrate our property driven hardware security solution for proving isolation, detecting timing channel, eliminating hardware Trojan, and enforcing security related statistical properties.","PeriodicalId":323077,"journal":{"name":"2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116093747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging 棘手的bug vs.智能工具- L2/L3缓存验证使用系统Verilog, UVM和Verdi事务调试

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.15

V. Viswanathan, Juliet Runhaar, Doug Reed, Jun Zhao

引用次数: 2

An Efficient Scenario Based Testing Methodology Using UVM 一种基于场景的UVM测试方法

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.14

Khaled Fathy, K. Salah

引用次数: 5

Hardware-Based Workload Forensics and Malware Detection in Microprocessors 微处理器中基于硬件的工作负载取证和恶意软件检测

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.20

Liwei Zhou, Y. Makris

{"title":"Hardware-Based Workload Forensics and Malware Detection in Microprocessors","authors":"Liwei Zhou, Y. Makris","doi":"10.1109/MTV.2016.20","DOIUrl":"https://doi.org/10.1109/MTV.2016.20","url":null,"abstract":"We investigate the possibility of performing workload forensics and/or malware detection in microprocessors through exclusively hardware-based methodologies. Specifically, we first introduce a general architecture which a hardware-based forensics or malware detection method would need to follow, as well as the various processor-level information which could potentially be harnessed to ensure system security and/or integrity. In contrast to traditional forensics and/or malware detection methods implemented at the operating system (OS) and/or the hypervisor level, whose data logging and monitoring systems are vulnerable to spoofing attacks at the same level, moving implementation to hardware ensures immunity to such attacks. This work focuses on two recent incarnations of this general concept, illustrating the effectiveness of hardware-based forensics and/or malware detection. Several other recent methods related to this topic are also discussed. Experimental results corroborate that even a low-cost hardware implementation can facilitate highly successful forensics analysis and/or malware detection, while taking advantage of its innate immunity to software-based attacks.","PeriodicalId":323077,"journal":{"name":"2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122168710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Case Study: Pre-Silicon SoC RAS Validation for NoC Server Processor 案例研究:NoC服务器处理器的预硅SoC RAS验证

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.26

Senwen Kan, Matthew Lam, Tyler Porter, Jennifer Dworak

引用次数: 3

Fake CPU: A Flexible and Simulation Cost-Effective UVC for Testing Shared Caches 假CPU:一个灵活和模拟成本效益的UVC测试共享缓存

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.13

S. Quirem, Prasad Krishna Saravu

引用次数: 1

Transaction Level Power Modeling (TLPM) Methodology 事务级功率建模(TLPM)方法

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.21

Amr B. Darwish, M. El-Moursy, M. Dessouky

引用次数: 3

2.5D/3D Integration Technologies for Circuit Obfuscation 电路混淆的2.5D/3D集成技术

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.17

Yang Xie, Chongxi Bao, Yuntao Liu, Ankur Srivastava

引用次数: 8

Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker 多处理器内存记分牌:一个多处理器内存排序和数据一致性检查器

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.16

Prasad Krishna Saravu

引用次数: 0

Echoing the "Generality Concept" through the Bus Functional Model Architecture in Universal Verification Environments 通过通用验证环境中的总线功能模型体系结构响应“通用概念”

2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2016-12-01 DOI: 10.1109/MTV.2016.18

Ahmed El-Yamany

{"title":"Echoing the \"Generality Concept\" through the Bus Functional Model Architecture in Universal Verification Environments","authors":"Ahmed El-Yamany","doi":"10.1109/MTV.2016.18","DOIUrl":"https://doi.org/10.1109/MTV.2016.18","url":null,"abstract":"Verification acts as a major milestone in any semiconductorindustry. With the huge investment and time-to-marketpressure, the verification process must be expeditious and decisive. Since the introduction of the Universal Verification Environment(UVM) by Accellera in 2011, new techniques and packages aredeliberately added to facilitate the process of verification andgeneralize it as the UVM originally meant to act in order to, emphasize the reusability concept. This paper proposes a newlayer to be added in the UVM generic environments when thetheme of verification is the same for each intellectual property (IP) with only diversity in interfaces. We validate our concept througha generic verification environment for flash memory controllerswe proposed in a previous work. The paper uses the generalityconcept introduced to create an optimized generic (UVM) architecture to verify the main types of the flash memorycontrollers with much less effort and tediousness. This genericUVM architecture is developed to verify multiple protocols withgeneric-HOST-/Memory interfaces. The main type of memorycontrollers we are dealing with are the flash memory controllersas the Flex-One NAND, Open NAND Flash Interface–ONFI-,Embedded Multi-Media Card (e.MMC), Universal Flash Storage(UFS) and the SD-CARD memory controller examined with –opensource WB interface.","PeriodicalId":323077,"journal":{"name":"2016 17th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128950795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0