2020 Forum for Specification and Design Languages (FDL)最新文献

Synchronized Shared Memory and Procedural Abstraction: Towards a Formal Semantics of Blech 同步共享内存与过程抽象:面向Blech的形式语义

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232942

Friedrich Gretz, Franz-Josef Grosch, Michael Mendler, Stephan Scheele

{"title":"Synchronized Shared Memory and Procedural Abstraction: Towards a Formal Semantics of Blech","authors":"Friedrich Gretz, Franz-Josef Grosch, Michael Mendler, Stephan Scheele","doi":"10.1109/FDL50818.2020.9232942","DOIUrl":"https://doi.org/10.1109/FDL50818.2020.9232942","url":null,"abstract":"Traditional imperative synchronous programming languages heavily rely on a strict separation between data memory and communication signals. Signals can be shared between computational units but cannot be overwritten within a synchronous reaction cycle. Memory can be destructively updated but cannot be shared between concurrent threads. This incoherence makes traditional imperative synchronous languages cumbersome for the programmer. The recent definition of sequentially constructive synchronous languages offers an improvement. It removes the separation between data memory and communication signals and unifies both through the notion of clock synchronised shared memory. However, it still depends on global causality analyses which precludes procedural abstraction. This complicates reuse and composition of software components. This paper shows how procedural abstraction can be accommodated inside the sequentially constructive model of computation. We present the Sequentially Constructive Procedural Language (SCPL) and its semantic theory of policy-constructive synchronous processes. SCPL supports procedural abstractions using policy interfaces to ensure that procedure calls are memory safe, wait-free and their scheduling is determinate and causal. At the same time, a policy interface constrains the level of freedom for the implementation and subsequent refactoring of a procedure. As a result, policies enable separate compilation and composition of procedures. We present our extensions abstractly as a formal semantics for SCPL and motivate it concretely in the context of the open-source, embedded, real-time language Blech.","PeriodicalId":322690,"journal":{"name":"2020 Forum for Specification and Design Languages (FDL)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123295471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Hard Real Time Demonstrator for Dynamic Ticks and Timed SCCharts 动态刻度和定时scchart的硬实时演示

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232943

Andreas Boysen, Alexander Schulz-Rosengarten, R. V. Hanxleden

{"title":"A Hard Real Time Demonstrator for Dynamic Ticks and Timed SCCharts","authors":"Andreas Boysen, Alexander Schulz-Rosengarten, R. V. Hanxleden","doi":"10.1109/FDL50818.2020.9232943","DOIUrl":"https://doi.org/10.1109/FDL50818.2020.9232943","url":null,"abstract":"Synchronous programming languages, such as Esterel, Lustre, SCADE or SCCharts, have been developed for designing reactive systems. They abstract from computation times and assume that outputs are synchronous with their inputs. This leads to a deterministic semantics, without race conditions, which makes synchronous languages particularly suitable for safety-critical systems. However, even though synchronous languages have been designed with real-time applications in mind, the handling of physical time is traditionally left to the execution environment. This makes e. g. the expression of arbitrary timeouts difficult and may lead to excessive “busy waiting” computations. The recent proposal of dynamic ticks alleviates this by making physical time a first-class citizen within the synchronous programming model. In this paper, we explore and demonstrate the practical merits of dynamic ticks, including improved timing accuracy and reduced computational requirements, in the context of Timed SCCharts. As demonstration platform, we present a hardware/software platform that involves two stepper motors whose operation must be synchronized at microsecond accuracy to avoid physical damage.","PeriodicalId":322690,"journal":{"name":"2020 Forum for Specification and Design Languages (FDL)","volume":"28 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125700153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Algebra of Deterministic Propositional Acceptance Automata (DPAA) 确定性命题接受自动机(DPAA)代数

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232945

Aurélien Lamercerie, B. Caillaud

引用次数: 1

Beyond real number modeling: Comparison of analog modeling approaches. 超越实数建模:模拟建模方法的比较。

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232932

W. Scherr, K. Einwich

{"title":"Beyond real number modeling: Comparison of analog modeling approaches.","authors":"W. Scherr, K. Einwich","doi":"10.1109/FDL50818.2020.9232932","DOIUrl":"https://doi.org/10.1109/FDL50818.2020.9232932","url":null,"abstract":"In the last few years, several approaches were presented to model analog behavior using digital description languages. It was shown that these easily outperform, for abstract behaviour models, the classic SPICE simulation approaches and can run on digital, event-based simulators. But which is really the most efficient of these? Thus, this work aims to compare the most common “digital” approaches. At first, it focus on generating models based on directed real-type signals only - the so called real number models (RNM). Using a classic filter example, it presents one model in SystemVerilog and one model in SystemC. For both setups the simulation performance is evaluated. Next, to generalize and simplify the modeling process, alternative solutions are implemented. The System Verilog model is refined by a novel proposal, defining linear elements and a resolved, bidirectional signal type called EEnet. In contrast, a model is implemented in SystemC-AMS using standard elements based on electrical linear networks. The execution time of these models is measured as well. All results, generated on the very same hardware and operating system, are collected and presented in a single diagram for comparison. Although SystemC and SystemC-AMS models can outperform their related implementations in SystemVerilog in several aspects, this work points out some potential room for improvement. The results also allow to state some general rules for modeling and simulation.","PeriodicalId":322690,"journal":{"name":"2020 Forum for Specification and Design Languages (FDL)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114232349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Bringing Uncertainties into System Simulation: A SystemC AMS Case Study 将不确定性引入系统仿真:一个SystemC AMS案例研究

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9233008

Carna Zivkovic, C. Grimm, J. Kölsch, D. Short, M. Ferstl, Dirk Denger, D. Krems, A. Barisic

引用次数: 0

Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study 处理器验证的高效跨级测试:RISC- V案例研究

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232941

V. Herdt, Daniel Große, E. Jentzsch, R. Drechsler

引用次数: 18

Machine Learning in Compilers: Past, Present and Future 编译器中的机器学习:过去，现在和未来

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232934

Hugh Leather, Chris Cummins

{"title":"Machine Learning in Compilers: Past, Present and Future","authors":"Hugh Leather, Chris Cummins","doi":"10.1109/FDL50818.2020.9232934","DOIUrl":"https://doi.org/10.1109/FDL50818.2020.9232934","url":null,"abstract":"Writing optimising compilers is difficult. The range of programs that may be presented to the compiler is huge and the systems on which they run are complex, heterogeneous, non-deterministic, and constantly changing. The space of possible optimisations is also vast, making it very hard for compiler writers to design heuristics that take all of these considerations into account. As a result, many compiler optimisations are out of date or poorly tuned. Near the turn of the century it was first shown how compilers could be made to automatically search the optimisation space, producing programs far better optimised than previously possible, and without the need for compiler writers to worry about architecture or program specifics. The searches, though, were slow, so in the years that followed, machine learning was developed to learn heuristics from the results of previous searches so that thereafter the search could be avoided and much of the benefit could be gained in a single shot. In this paper we will give a retrospective of machine learning in compiler optimisation from its earliest inception, through some of the works that set themselves apart, to today's deep learning, finishing with our vision of the field's future.","PeriodicalId":322690,"journal":{"name":"2020 Forum for Specification and Design Languages (FDL)","volume":"46 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114135631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

A Language for Deterministic Coordination Across Multiple Timelines 一种跨多时间线的确定性协调语言

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232939

Marten Lohstroh, Christian Menard, Alexander Schulz-Rosengarten, Matthew Weber, J. Castrillón, Edward A. Lee

引用次数: 9

Supervisory Control for Dynamic Feature Configuration in Product Lines 生产线动态特征配置的监控

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232937

M. Reniers, S. Thuijsman

引用次数: 4

ComPy-Learn: A toolbox for exploring machine learning representations for compilers ComPy-Learn:一个用于探索编译器机器学习表示的工具箱

2020 Forum for Specification and Design Languages (FDL) Pub Date : 2020-09-15 DOI: 10.1109/FDL50818.2020.9232946

Alexander Brauckmann, Andrés Goens, J. Castrillón

引用次数: 5