2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献

On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations 片上监测和补偿方案与细颗粒体偏置，鲁棒和节能的操作

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7428045

Islam A. K. M. Mahfuzul, H. Onodera

引用次数: 3

Generating high coverage tests for SystemC designs using symbolic execution 使用符号执行为SystemC设计生成高覆盖率的测试

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7428006

Bin Lin, Zhenkun Yang, Kai Cong, Fei Xie

引用次数: 15

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling 具有热感知动态电压和频率缩放的可测试和可调试的双核系统

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7427980

L. Lu, C. Chang, Zhao-Hong Chen, B. Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, L. Chiou, Soon-Jyh Chang, Chien-Hung Tsai, C. Chen, Jai-Ming Lin

引用次数: 3

Security analysis on consumer and industrial IoT devices 消费和工业物联网设备的安全分析

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7428064

Jacob Wurm, Khoa Hoang, Orlando Arias, A. Sadeghi, Yier Jin

引用次数: 233

Netlist reverse engineering for high-level functionality reconstruction 用于高级功能重建的网表逆向工程

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7428086

Travis Meade, Shaojie Zhang, Yier Jin

引用次数: 64

A mutual auditing framework to protect IoT against hardware Trojans 一个相互审计框架，以保护物联网免受硬件木马

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7427991

Chen Liu, P. Cronin, Chengmo Yang

引用次数: 21

Accurate remaining range estimation for Electric vehicles 电动汽车剩余里程的精确估计

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7428106

Joonki Hong, Sang-Jae Park, N. Chang

{"title":"Accurate remaining range estimation for Electric vehicles","authors":"Joonki Hong, Sang-Jae Park, N. Chang","doi":"10.1109/ASPDAC.2016.7428106","DOIUrl":"https://doi.org/10.1109/ASPDAC.2016.7428106","url":null,"abstract":"EVs (Electric vehicle) generally have only around 22% driving ranges compared with ICEVs (Internal combustion engine vehicle) with a similar price range. Running out of the EV battery SoC (State of charge) while driving gives the same inconvenience as a vehicle breakdown. In this paper, we emphasize that an accurate remaining range estimation can efficiently mitigate the range anxiety of EV drivers. Most EV drivers reserve 30% of the on-dash estimated remaining range gauge of their EV because they do not trust the current remaining range estimation accuracy of production EVs. In other words, an accurate remaining range estimation is equivalent to increasing the EV battery capacity up to 30%. Just like the analogous concepts used in the power estimation of digital circuits, a model-based remaining range estimation consists of the two consecutive steps, a driving profile estimation and a power consumption estimation using the power model. In this paper, we focus on increasing the accuracy of the power model. We come up with a hybrid modeling methodology combining a physics equation based model with empirical data. We validate the accuracy of the hybrid model in the remaining range estimation with the target EV. We collect the power consumption, velocity, road inclination, etc. of the EV in every half second with an onboard monitoring system, a perform multivariable linear regression and create an accurate EV power model. The proposed remaining range estimation yields only 2.52% error while the state-of-the-art model-based EV remaining range estimation shows 9.33% error when the same future route and speed estimation are given.","PeriodicalId":320183,"journal":{"name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114277544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization 后置优化中降低功耗的松耦合多位触发器的设计与分配

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7428022

Hyoungseok Moon, Taewhan Kim

{"title":"Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization","authors":"Hyoungseok Moon, Taewhan Kim","doi":"10.1109/ASPDAC.2016.7428022","DOIUrl":"https://doi.org/10.1109/ASPDAC.2016.7428022","url":null,"abstract":"Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. The obstacles that hinder the merging process for multi-bit flip-flops are (1) the input and output timing constraint on every flip-flop, (2) the area constraint on every partitioned bin in the placement plane, and (3) the routing capacity constraint on every bin edge. This work tries to eliminate constraint-1 and constraint-2 so that a full benefit of multi-bit flip-flops can be reaped. Precisely, rather than using the conventional structure of multi-bit flip-flops, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space in constraint-2 and no need to check timing in constraint-1. Utilizing LC-MBFFs, we propose a routability and clock-tree driven multi-bit flip-flop allocation algorithm, which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.50% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%.","PeriodicalId":320183,"journal":{"name":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121879767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

STORM: A nonlinear model order reduction method via symmetric tensor decomposition STORM:一种基于对称张量分解的非线性模型降阶方法

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7428070

Jian Deng, Haotian Liu, Kim Batselier, Yu-Kwong Kwok, N. Wong

引用次数: 8

Architecture design with STT-RAM: Opportunities and challenges 采用STT-RAM的建筑设计:机遇与挑战

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2016-03-10 DOI: 10.1109/ASPDAC.2016.7427997

Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung H. Kang, Yuan Xie

引用次数: 33