2018 International Conference on High Performance Computing & Simulation (HPCS)最新文献

Seamless GPU Evaluation of Smart Expression Templates 智能表达式模板的无缝GPU评估

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-16 DOI: 10.1109/HPCS.2018.00045

Baptiste Wicht, Andreas Fischer, J. Hennebert

引用次数: 0

Symbolic Matrix Multiplication for Multithreaded Sparse GEMM Utilizing Sparse Matrix Formats 基于稀疏矩阵格式的多线程稀疏GEMM符号矩阵乘法

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-16 DOI: 10.1109/HPCS.2018.00088

Marcel Richter, G. Rünger

{"title":"Symbolic Matrix Multiplication for Multithreaded Sparse GEMM Utilizing Sparse Matrix Formats","authors":"Marcel Richter, G. Rünger","doi":"10.1109/HPCS.2018.00088","DOIUrl":"https://doi.org/10.1109/HPCS.2018.00088","url":null,"abstract":"Sparse matrices are exploited in many problems from scientific computing and, thus, their efficient implementation is crucial for the overall performance of the problems. Three sparse matrix formats, such as Compressed Sparse Row Storage, Block Sparse Row Storage and Ellpack-Itpack, have been proposed to support an efficient storage and access to sparse matrices. A specific challenge is to implement sparse matrices on parallel platforms and to support efficient access within parallel algorithms. This article is a contribution towards the efficient parallel execution of a multi-threaded general matrix-matrix multiplication (GEMM) using sparse matrices. Major considerations are based on the benefit and overhead of a symbolic GEMM prior to the sparse GEMM operation to obtain information about the result matrix structure. Hence, overhead regarding sorting, merging of data structures and memory allocation routines can be minimized to improve the runtime performance. Multi-threaded GEMM implementations are studied for different storage formats and their performance is investigated for a broad range of sparse test matrices on recent multicore architectures. A constraint of our approach is that the sparse GEMM should be performed such that the sparse matrix format is an invariant property and the result matrix of the GEMM operation is provided in the same format without matrix format changes.","PeriodicalId":308138,"journal":{"name":"2018 International Conference on High Performance Computing & Simulation (HPCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133549028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Identifying the Temporal Structure of Parallel Application Computation Phases 确定并行应用程序计算阶段的时间结构

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00087

D. Dosimont, Harald Servat, M. Wagner, Judit Giménez, Jesús Labarta

{"title":"Identifying the Temporal Structure of Parallel Application Computation Phases","authors":"D. Dosimont, Harald Servat, M. Wagner, Judit Giménez, Jesús Labarta","doi":"10.1109/HPCS.2018.00087","DOIUrl":"https://doi.org/10.1109/HPCS.2018.00087","url":null,"abstract":"Performance analysis tools are essential to help developers improve the performance of their parallel applications. These tools have widely embraced graphical representations to ease the analyst experience. However, they might mislead the analysis if using questionable aggregation techniques, especially when dealing with much data in timelines. In this paper, we have put efforts to demonstrate the value of information theory topics when applied to performance analysis. To this end, we extend a previously designed tool named folding which focuses on a detailed exploration of computation phases using trace files containing instrumented and sampled information. We design appropriate representations for the folding output by adopting an innovative aggregation technique based on information theory. As we will demonstrate through the paper, the original implementation of this tool may hinder the analysis by the introduction of some artifacts as a result of the chosen aggregation techniques. Additionally, we extend the folding tool to provide a decent analysis overview to start the analysis. Last, but not least, we successfully apply the new flow to two in-production HPC applications and characterize their performance behavior.","PeriodicalId":308138,"journal":{"name":"2018 International Conference on High Performance Computing & Simulation (HPCS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124913625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Strong Security Guarantees: From Alloy to Coq (Research Poster) 强大的安全保障:从合金到Coq(研究海报)

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00167

Salwa Souaf, F. Loulergue

引用次数: 1

A New Beta Chaotic Watermarking Scheme based on DWT and SVD 一种基于小波变换和奇异值分解的混沌水印算法

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00107

Houda Soudan, R. Ejbali, M. Zaied

引用次数: 1

Challenges for Reliable and Large Scale Evaluation of Android Malware Analysis Android恶意软件分析可靠和大规模评估的挑战

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00173

Jean-François Lalande, Valérie Viet Triem Tong, M. Leslous, Pierre Graux

引用次数: 5

Madeus: A Formal Deployment Model Madeus:一个正式的部署模型

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00118

Maverick Chardet, Hélène Coullon, Dimitri Pertin, Christian Pérez

{"title":"Madeus: A Formal Deployment Model","authors":"Maverick Chardet, Hélène Coullon, Dimitri Pertin, Christian Pérez","doi":"10.1109/HPCS.2018.00118","DOIUrl":"https://doi.org/10.1109/HPCS.2018.00118","url":null,"abstract":"Distributed software architecture is composed of multiple interacting modules, or components. Deploying such software consists in installing them on a given infrastructure and leading them to a functional state. However, since each module has its own life cycle and might have various dependencies with other modules, deploying such software is a very tedious task, particularly on massively distributed and heterogeneous infrastructures. To address this problem, many solutions have been designed to automate the deployment process. In this paper, we introduce Madeus, a component-based deployment model for complex distributed software. Madeus accurately describes the life cycle of each component by a Petri net structure, and is able to finely express the dependencies between components. The overall dependency graph it produces is then used to reduce deployment time by parallelizing deployment actions. While this increases the precision and performance of the model, it also increases its complexity. For this reason, the operational semantics needs to be clearly defined to prove results such as the termination of a deployment. In this paper, we formally describe the operational semantics of Madeus, and show how it can be used in a use- case: the deployment of a real and large distributed software (i.e., OpenStack).","PeriodicalId":308138,"journal":{"name":"2018 International Conference on High Performance Computing & Simulation (HPCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128770190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A Novel Framework for the Seamless Integration of FPGA Accelerators with Big Data Analytics Frameworks in Heterogeneous Data Centers 异构数据中心中FPGA加速器与大数据分析框架无缝集成的新框架

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00090

I. Stamelos, Elias Koromilas, C. Kachris, D. Soudris

引用次数: 5

Evaluating the Intel Skylake Xeon Processor for HPC Workloads 评估英特尔Skylake至强处理器的HPC工作负载

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00064

S. Hammond, C. Vaughan, C. Hughes

{"title":"Evaluating the Intel Skylake Xeon Processor for HPC Workloads","authors":"S. Hammond, C. Vaughan, C. Hughes","doi":"10.1109/HPCS.2018.00064","DOIUrl":"https://doi.org/10.1109/HPCS.2018.00064","url":null,"abstract":"Despite significant advances in the porting of scientific applications to novel architectures such as compute-optimized graphics processors, many-core processor/accelerators and, even special-purpose function units, the vast majority of scientific calculations are still performed on high-performance, commodity server processors. Even in the cases of applications which have been ported to new architectures, frequent serial sections still require strong server-class processor cores to compute as fast as possible. In this paper we report on a set of benchmark studies which evaluate Intel's latest Skylake Xeon server processor. Skylake represents a significant change in the Xeon product line with wider SIMD vector units, a redesigned cache architecture, and, an increased number of memory channels. The wider vector units provide 2x improvement for some compute-intensive applications and the combined memory changes can provide close to 2x the memory bandwidth. We evaluate these new hardware features on several HPC-relevant mini-applications and benchmarks, including, STREAM, LULESH, XSBench, HPCG and SW4Lite. Together, the new hardware functions provide up to 1.8x speedup on HPC benchmark codes when compared with the previous generation Haswell processor core, providing much greater utility to a broader range of HPC applications that rely on this class of compute node.","PeriodicalId":308138,"journal":{"name":"2018 International Conference on High Performance Computing & Simulation (HPCS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129235853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Hybrid Feature Extraction for Palmprint-Based User Authentication 基于掌纹的用户认证混合特征提取

2018 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2018-07-01 DOI: 10.1109/HPCS.2018.00104

Agata Giełczyk, M. Choraś, R. Kozik

引用次数: 4