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2016 International Conference on Applied Electronics (AE)最新文献

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Analytical comparison of topology configuration of wireless power transfer system 无线电力传输系统拓扑结构的分析比较
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577252
V. Jaros, P. Drgona, B. Kozacek, M. Piri
{"title":"Analytical comparison of topology configuration of wireless power transfer system","authors":"V. Jaros, P. Drgona, B. Kozacek, M. Piri","doi":"10.1109/AE.2016.7577252","DOIUrl":"https://doi.org/10.1109/AE.2016.7577252","url":null,"abstract":"This article deals with the description of topology configuration of wireless energy transfer system. Wireless energy transfer systems are used in several applications areas as is wireless charging accumulators in electric vehicles, charging batteries in mobiles, in lighting applications and other. This article is focused on wireless charging accumulators in electric vehicles, which the main quality indicators are high transmitted power, high efficiency and the transmission distance in range of the ground clearance of standard vehicles. There are described two topologies, first is series - series compensated system and second is series - parallel compensated system.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122900129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Model of integration of embedded systems via CoAP protocol of Internet of Things 基于物联网CoAP协议的嵌入式系统集成模型
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577273
P. Peniak, M. Franeková
{"title":"Model of integration of embedded systems via CoAP protocol of Internet of Things","authors":"P. Peniak, M. Franeková","doi":"10.1109/AE.2016.7577273","DOIUrl":"https://doi.org/10.1109/AE.2016.7577273","url":null,"abstract":"This article deals with Internet of Things as an integration platform for embedded systems. The problem of traditional hierarchical communication is challenged by direct peer-to-peer communication model among various embedded devices. CoAP protocol is selected as a potential candidate to meet that requirements and enable overall integration among embedded systems and Cloud systems. In addition, there is evaluated an option to use dedicated IoT integration gateway to enable smooth communication of devices with various maturity level protocols. IoT gateway can support protocol translation and various proxy functions for connection with Cloud systems.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125631886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Fractional-order high-pass filter with electronically adjustable parameters 带有电子可调参数的分数阶高通滤波器
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577253
J. Jerabek, R. Sotner, Jan Dvorak, L. Langhammer, J. Koton
{"title":"Fractional-order high-pass filter with electronically adjustable parameters","authors":"J. Jerabek, R. Sotner, Jan Dvorak, L. Langhammer, J. Koton","doi":"10.1109/AE.2016.7577253","DOIUrl":"https://doi.org/10.1109/AE.2016.7577253","url":null,"abstract":"This paper presents possible solution of fractional-order high-pass filter (FHPF) with electronically adjustable order between 1 and 2 and also with electronically adjustable pole frequency. It is based on well-known Follow-the-Leader Feedback (FLF) topology adjusted for utilization with operational transconductance amplifiers (OTAs) and adjustable current amplifiers (ACAs). This 3rd-order topology is used in order to approximate FHPF response in particular frequency band of interest. Design is supported by Pspice simulations for three particular values of the filter's order (1.25, 1.5, 1.75) and for several values of pole frequency. Moreover, simulation results with two different approximations are compared.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114232159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Long Term Evolution networks planning 长期演进网络规划
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577239
Ján Cerný, Jiří Masopust
{"title":"Long Term Evolution networks planning","authors":"Ján Cerný, Jiří Masopust","doi":"10.1109/AE.2016.7577239","DOIUrl":"https://doi.org/10.1109/AE.2016.7577239","url":null,"abstract":"This work deals with 4th Generation Long Term Evolution (LTE) standard for mobile telecommunication. LTE comes with new approaches how to increase speed and stability of wireless data transmission. Planning these networks involves many complex tasks, therefore advanced software tools are needed. The mostly used are Atoll or ASSET. This simulation described in the end of this paper is attempting to demonstrate the most important principles of the planning process.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115937273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
FinFET based 4-BIT input XOR/XNOR logic circuit 基于4位FinFET输入的XOR/XNOR逻辑电路
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577277
Sarada Musala, Avireni Srinivasulu
{"title":"FinFET based 4-BIT input XOR/XNOR logic circuit","authors":"Sarada Musala, Avireni Srinivasulu","doi":"10.1109/AE.2016.7577277","DOIUrl":"https://doi.org/10.1109/AE.2016.7577277","url":null,"abstract":"In this paper a structure for direct 4-BIT XOR/XNOR logic cell is proposed. This structure is proposed using pass transistor logic with FinFETs. This structure has less delay for the reason that its critical path consists of a minimum number of transistors. The basic advantage of this circuit is their symmetry in the logic. This design has a full voltage swing at the outputs and hence it has the good driving capability. The proposed design produces perfect outputs, even at low voltages and at high frequencies with the lesser transistor count. The proposed design is simulated using Cadence 20 nm FinFET technology at various supply voltages assorting from +0.6 V to +0.9 V. The simulation results illustrate that the proposed design has less delay and as well as less power consumption.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132323873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new high efficiency high power factor ZVT bridgeless PFC converter 一种新型高效率高功率因数ZVT无桥PFC变换器
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577264
M. Mahdavi, Hamid Torkkhah
{"title":"A new high efficiency high power factor ZVT bridgeless PFC converter","authors":"M. Mahdavi, Hamid Torkkhah","doi":"10.1109/AE.2016.7577264","DOIUrl":"https://doi.org/10.1109/AE.2016.7577264","url":null,"abstract":"In this paper, a new zero voltage transition (ZVT) bridgeless PFC converter with high power factor and high efficiency is presented. The proposed converter has not any extra voltage stresses on semiconductor elements. Main switches of the converter are switched under zero voltage (ZV) condition. Also the auxiliary switch is turned on under zero current (ZC) and turned off under zero voltage and current (ZVZC) condition. Due to use of bridgeless topology and soft switching technique simultaneously the converter's efficiency is higher than conventional counterpart. Also the proposed converter does not need the float gate driver. The operation of proposed converter is analyzed theoretically and the operation modes are presented. The design considerations are explained by a design example. The proposed converter is simulated by PSIM software to show the validity of theoretical analysis. The simulation results are compared with theoretical waveforms. The efficiency of simulation in ORCAD software shows 2% improvement in comparison with conventional PFC boost converter.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation and control of FLC converters for UPS systems UPS系统FLC变换器的仿真与控制
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577238
Jiří Brychcín, T. Kosan, D. Janik, Z. Peroutka
{"title":"Simulation and control of FLC converters for UPS systems","authors":"Jiří Brychcín, T. Kosan, D. Janik, Z. Peroutka","doi":"10.1109/AE.2016.7577238","DOIUrl":"https://doi.org/10.1109/AE.2016.7577238","url":null,"abstract":"This paper is focused on simulation of the diesel or gas electric central, which is used for uninterruptible power supply (UPS) with permanent magnet synchronous generator (PMSG) and flying capacitor converters (FLC).","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126850207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of failure mode, effect and Criticality Analysis 失效模式、影响及临界分析研究
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-29 DOI: 10.1109/AE.2016.7577249
Paul Chang, Yi-Lin He
{"title":"Study of failure mode, effect and Criticality Analysis","authors":"Paul Chang, Yi-Lin He","doi":"10.1109/AE.2016.7577249","DOIUrl":"https://doi.org/10.1109/AE.2016.7577249","url":null,"abstract":"As machining tool systems become increasingly more complicated, the improvement of system scale and functions, increases the probability of system failure. To avoid human injuries caused by system failure, improve system reliability, and enhance the management of system failure and risk control, reliability analysis technology, called FMECA, has been applied many industries since the 1950s. This paper, first, introduces a brief history of FMECA and the current international standard. Second, the core concept and implementation procedure of FMECA will be presented. Finally, the advantages and disadvantages of FMECA and conclusions are provided.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131974082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Using VHDL-AMS to simulate aging behavior of electronic components 利用VHDL-AMS模拟电子元件的老化行为
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-01 DOI: 10.1109/AE.2016.7577248
G. Hofmann, V. Georgiev
{"title":"Using VHDL-AMS to simulate aging behavior of electronic components","authors":"G. Hofmann, V. Georgiev","doi":"10.1109/AE.2016.7577248","DOIUrl":"https://doi.org/10.1109/AE.2016.7577248","url":null,"abstract":"Reliability of electronics is in the automotive industry very important. The average age of cars in Germany was 9 years at 2015.i Normally the life time is evaluated by the environmental test according ISO 16750. The content of this paper is to contribute that computer simulation of aging is a possible way to evaluate electronic circuits in the define phase. For this reason a VHDL-AMS simulation models is used to model aging behavior of a resistor.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic duty-cycle limitation of the boost DC/DC converter allowing maximal output power operations 允许最大输出功率操作的升压DC/DC变换器的动态占空比限制
2016 International Conference on Applied Electronics (AE) Pub Date : 2016-09-01 DOI: 10.1109/AE.2016.7577268
V. Michal
{"title":"Dynamic duty-cycle limitation of the boost DC/DC converter allowing maximal output power operations","authors":"V. Michal","doi":"10.1109/AE.2016.7577268","DOIUrl":"https://doi.org/10.1109/AE.2016.7577268","url":null,"abstract":"This paper describes the concept of the dynamic duty-cycle limiter of the boost dc-dc converter. Duty-cycle limitation in boost converters is usually used to protect the bottom switch against an excessive current, and also to avoid instability occurring at high duty-cycle operations. Compared to fixed limitation, dynamic limiter enables to detect and maintain maximal possible output voltage VMAX, when desired output voltage cannot be provided e.g. due to excessive load current or increased resistance of the switches. This feature allows to extend the operation range of the converter and powered device. Developed method applies to low power converters, and it is based on the power balance condition detection circuit. This detection is realized via simple and low consumption voltage sensing. Paper presents description of the method, circuit implementation and shows simulated results obtained with integrated 0.13μm CMOS boost dc-dc converter.","PeriodicalId":306881,"journal":{"name":"2016 International Conference on Applied Electronics (AE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125114009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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