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Proceedings Tenth International Conference on VLSI Design最新文献

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A hierarchical technique for minimum-width layout of two-dimensional CMOS cells 二维CMOS单元最小宽度布局的层次化技术
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.567954
Avaneendra Gupta, J. Hayes
{"title":"A hierarchical technique for minimum-width layout of two-dimensional CMOS cells","authors":"Avaneendra Gupta, J. Hayes","doi":"10.1109/ICVD.1997.567954","DOIUrl":"https://doi.org/10.1109/ICVD.1997.567954","url":null,"abstract":"We present a hierarchical technique, based on integer linear programming (ILP), to generate area-efficient layouts of relatively large complex CMOS cells in the two-dimensional (2-D or multi-row) style. First, the CMOS circuit is partitioned into subcircuits called clusters. Next, the set of all minimum-width 1-D placements (chain covers) are generated for each cluster and form the input to the ILP model. The model aims at selecting exactly one cover for each cluster such that the overall 2-D cell width is minimized. In the process, all possible diffusion sharing between transistor chains belonging to clusters are considered; the inter-row connections that contribute to the overall cell width are also reduced. Experimental results demonstrate that the technique reduces run times by several orders of magnitude over non-hierarchical methods, and yields optimal or near-optimal layouts in most cases.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121026098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A parallel architecture for video compression 视频压缩的并行架构
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568084
P. Bhattacharjee, Sajal K. Das, D. Saha, D. Roychowdhury, P. P. Chaudhuri
{"title":"A parallel architecture for video compression","authors":"P. Bhattacharjee, Sajal K. Das, D. Saha, D. Roychowdhury, P. P. Chaudhuri","doi":"10.1109/ICVD.1997.568084","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568084","url":null,"abstract":"This paper reports a parallel algorithm for compression/decompression of video data files. The algorithm can be easily implemented on a parallel pipelined architecture that can support on-line compression/decompression. The hardware implementing the architecture achieves a throughput of 30 frames per second with frame size of 352/spl times/272 pixels.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127347500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A general reconfiguration technique for fault tolerant processor architectures 容错处理器体系结构的通用重构技术
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568153
Eshwar Belani, R. Mittal
{"title":"A general reconfiguration technique for fault tolerant processor architectures","authors":"Eshwar Belani, R. Mittal","doi":"10.1109/ICVD.1997.568153","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568153","url":null,"abstract":"In this paper we present a new approach for fault tolerance in VLSI processor architectures. The reconfiguration technique is a general one in the sense that it can be applied to any arbitrary architecture with any number of spares each of which may be connected to an arbitrary number of processing elements. The technique is composed of two stages, local and global reconfiguration. In the local reconfiguration stage, faulty cells are maximally mapped onto adjacent spares. In the global stage, the shortest path from a faulty cell to a spare is found and the spare is \"propagated\" to the faulty site by the logical displacement of processing elements along that path.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A self-biased high performance folded cascode CMOS op-amp 一种自偏置高性能折叠级联CMOS运算放大器
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568171
P. Mandal, V. Visvanathan
{"title":"A self-biased high performance folded cascode CMOS op-amp","authors":"P. Mandal, V. Visvanathan","doi":"10.1109/ICVD.1997.568171","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568171","url":null,"abstract":"Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptibility of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded casode op amps, except for a small reduction in slew rate. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114416548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Behavioral array mapping into multiport memories targeting low power 行为阵列映射到多端口存储器目标低功耗
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568088
P. Panda, N. Dutt
{"title":"Behavioral array mapping into multiport memories targeting low power","authors":"P. Panda, N. Dutt","doi":"10.1109/ICVD.1997.568088","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568088","url":null,"abstract":"Off chip memories are typically used during behavioral synthesis to store large arrays that do not fit into on-chip registers. An important power-optimization problem that arises in this context is the minimization of signal transitions on the off-chip buses connecting the ASIC and the memory. We address the problem of system power reduction through transition count minimization on the multiported, memory's address buses when these arrays are accessed from memory at execution time. We exploit regularity and spatial locality in the memory accesses and determine a power-efficient mapping of behavioral array references to physical locations as well as ports of a multiport memory. Our experiments on several image processing benchmarks show significant power savings through reduced transition activity on the memory address buses, compared to a straightforward mapping scheme.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Low-power driven logic synthesis using accurate power estimation technique 低功耗驱动逻辑合成采用精确的功率估计技术
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568073
P. Patil, T. Chou, K. Roy, R. Roy
{"title":"Low-power driven logic synthesis using accurate power estimation technique","authors":"P. Patil, T. Chou, K. Roy, R. Roy","doi":"10.1109/ICVD.1997.568073","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568073","url":null,"abstract":"With the increasing use of portable computing and wireless communication systems, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Towards this end we introduce algebraic procedures for node extraction and factorization that target low power consumption in combinational logic circuits. A new cost function is also proposed for the sum-of-products representation of the expressions. This cost function is used to guide the power optimization procedures. The spatial and temporal correlations of signals were taken into account to gain accurate power estimation. The results show that an average of 10% saving was gained in power using logic synthesis with the proposed accurate power estimation technique, compared to area optimized designs. Results also show that the power dissipation of the circuit, synthesized assuming temporally uncorrelated primary inputs, can dissipate 75% more power than that of the circuits assuming temporally correlated inputs.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Faster fault simulation through distributed computing 通过分布式计算实现更快的故障模拟
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568181
C. Ravikumar, Vikas Jain, Anurag Dod
{"title":"Faster fault simulation through distributed computing","authors":"C. Ravikumar, Vikas Jain, Anurag Dod","doi":"10.1109/ICVD.1997.568181","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568181","url":null,"abstract":"In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors -test set partition and fault set partition. The sequential algorithm for fault simulation, used on individual nodes of the network, is based on a novel path compression technique proposed in this paper. We describe experimental results on a number of ISCAS '85 benchmark circuits.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130634022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
FAMAS: FAult Modeling via Adaptive Simulation 基于自适应仿真的故障建模
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568168
H. Jin, R. Iyer, M. Hsueh
{"title":"FAMAS: FAult Modeling via Adaptive Simulation","authors":"H. Jin, R. Iyer, M. Hsueh","doi":"10.1109/ICVD.1997.568168","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568168","url":null,"abstract":"This paper describes FAMAS-FAult Modeling via Adaptive Simulation: a software tool that models transient faults and evaluates their impact on latch error probabilities through fault injection. The tool integrates DESSIS (a device-physics-level simulator) and SPICE using an adaptive approach. The behavior of electron hole pairs is captured for semiconductor devices under ionic radiation. Changes in bias voltage due to current surge are taken into account in an iterative fashion during the process of fault model construction. Results show that in general, the adaptively simulated fault model results in higher latch error probabilities than the Messenger model under the same process and electrical conditions.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An enhanced genetic solution for scheduling, module allocation, and binding in VLSI design 一种用于VLSI设计中的调度、模块分配和绑定的增强遗传解决方案
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.567960
G. Grewal, T. C. Wilson
{"title":"An enhanced genetic solution for scheduling, module allocation, and binding in VLSI design","authors":"G. Grewal, T. C. Wilson","doi":"10.1109/ICVD.1997.567960","DOIUrl":"https://doi.org/10.1109/ICVD.1997.567960","url":null,"abstract":"This paper presents a novel approach to the high-level synthesis problems of scheduling, module allocation, and module binding for behavioral descriptions. A very general version of this problem is considered where modules may perform different operations in different numbers of control steps. These inherently interdependent problems are solved using an Enhanced Genetic Algorithm (EGA) which is both more robust and more efficient than the simple GA.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":" 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113948264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design for testability: today and in the future 为可测试性而设计:现在和将来
Proceedings Tenth International Conference on VLSI Design Pub Date : 1997-01-04 DOI: 10.1109/ICVD.1997.568096
T. Williams
{"title":"Design for testability: today and in the future","authors":"T. Williams","doi":"10.1109/ICVD.1997.568096","DOIUrl":"https://doi.org/10.1109/ICVD.1997.568096","url":null,"abstract":"Summary form only given. The author reviews the current techniques with a particular emphasis on today's Scan Designs. This entails distinguishing the differences between scan techniques, since all scans are not created equal! From this point the Testability Standards are discussed; these include the Boundary Scan activities and the Analog activities. Fault models are taking on more robust attributes, since the Stuck-At-Fault is necessary but not sufficient in today's technologies. The Delay Fault models are discussed with a comparison between a model which increases exponentially with gate count (Path Delay Fault) and one which increases linearly with gate count (Gate Delay Fault). Clearly, self-test is taking on an ever more important role which impacts both manufacturing testing and field system testing. The popular self-testing design techniques are shown. The interaction of testing and synthesis is discussed with a view on delay. Finally, the role of testing is explored in the new design environments which includes Hardware and Software Codesign.","PeriodicalId":303635,"journal":{"name":"Proceedings Tenth International Conference on VLSI Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126538982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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