2019 Seventh International Symposium on Computing and Networking (CANDAR)最新文献_第4页

Framework for Detecting Control Command Injection Attacks on Industrial Control Systems (ICS) 工业控制系统控制命令注入攻击检测框架

2019 Seventh International Symposium on Computing and Networking (CANDAR) Pub Date : 2019-11-01 DOI: 10.1109/CANDAR.2019.00035

Farhad Rasapour, Edoardo Serra, Hoda Mehrpouyan

引用次数: 2

Function Identification in Android Binaries with Deep Learning 基于深度学习的Android二进制文件函数识别

2019 Seventh International Symposium on Computing and Networking (CANDAR) Pub Date : 2019-11-01 DOI: 10.1109/CANDAR.2019.00019

Aizaz Sharif, M. Nauman

{"title":"Function Identification in Android Binaries with Deep Learning","authors":"Aizaz Sharif, M. Nauman","doi":"10.1109/CANDAR.2019.00019","DOIUrl":"https://doi.org/10.1109/CANDAR.2019.00019","url":null,"abstract":"Application security support has become a preference for the enterprise as cybersecurity threats have transferred from the network perimeter to the application layer in modern years. To ensure that the software is secure, organizations must test it before purchase or deployment and identify any flaws that may expose the organizations to vulnerabilities. Binary code analysis is a new method for application security testing and is transforming software security. Binary analysis aids in many important applications including automatically fixing vulnerable software and malware detection. Plenty of research has been done to improve binary analysis using datasets related to different computer platforms, new compilers, and new optimization techniques. However, there is a vast majority of Android users and since it is an open-source platform it is equally vulnerable to similar attacks as well. In this research, we propose to implement deep neural networks to solve an essential yet difficult problem in binary analysis. We solve the problem of function boundary identification, a pivotal first step in a lot of binary analysis techniques. Neural networks have experienced a renewal in the past few years, achieving breakthrough outcomes in various fields such as object detection, language translation, and speech recognition. Yet no specific research has explored their utility in Android binary analysis. We exhibit that convolutional neural networks can identify functions in binaries with greater accuracy than the current state-of-the-art methods. Our model will be trained on a dataset of bytecode extracted from Android binaries. The proposed methodology is tested and evaluated on the Drebin Malware Dataset which contains Android Malware applications coming from various malware families. With the presented model, we achieved an overall precision of 0.75, recall of 0.79 and the f1 score of 0.76 in the testing phase.","PeriodicalId":300306,"journal":{"name":"2019 Seventh International Symposium on Computing and Networking (CANDAR)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115868097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Benchmarks for FPGA-Targeted High-Level-Synthesis 针对fpga的高级合成基准

2019 Seventh International Symposium on Computing and Networking (CANDAR) Pub Date : 2019-11-01 DOI: 10.1109/CANDAR.2019.00038

H. M. Waidyasooriya, Yasuaki Iimura, M. Hariyama

{"title":"Benchmarks for FPGA-Targeted High-Level-Synthesis","authors":"H. M. Waidyasooriya, Yasuaki Iimura, M. Hariyama","doi":"10.1109/CANDAR.2019.00038","DOIUrl":"https://doi.org/10.1109/CANDAR.2019.00038","url":null,"abstract":"Recently, high-level synthesis (HLS) tools such as \"Intel FPGA SDK for OpenCL'\" and \"Xilinx SDAccel\" have been introduced to design FPGA accelerators. Those HLS tools use \"C language\" based environment to significantly reduce the design time. However, it is also important to know how much performance we can achieve using HLS tools. FPGA is a highly reconfigurable hardware and the performances are extremely different depending on the architecture. Performances also depend on the FPGA board, HLS software and firmware such as BSP (board support package). Therefore, benchmarking FPGAs is an extremely challenging task. This paper proposes a method to design benchmarks for FPGA-targeted HLS. The benchmarks are highly scalable and can be used for different FPGAs and compilers to obtain most of the potential performance. Evaluating four different FPGAs, we found that the single-precision floating-point computation performance varies from 17 GFLOPS to 3,955 GFLOPS depending on the operation and the FPGA. We have obtained 64% and 43% of the peak performance of single-precision computation for Arria 10 and Stratix 10 FPGAs respectively. The fixed-point computation performance heavily depends on the bit size and varies from 8 GOPS to 12,800 GOPS.","PeriodicalId":300306,"journal":{"name":"2019 Seventh International Symposium on Computing and Networking (CANDAR)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116220587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid Storage System to Achieve Efficient Use of Fast Memory Area 混合存储系统实现快速内存面积的有效利用

2019 Seventh International Symposium on Computing and Networking (CANDAR) Pub Date : 2019-11-01 DOI: 10.1109/CANDAR.2019.00016

Kazuichi Oe, T. Nanri

{"title":"Hybrid Storage System to Achieve Efficient Use of Fast Memory Area","authors":"Kazuichi Oe, T. Nanri","doi":"10.1109/CANDAR.2019.00016","DOIUrl":"https://doi.org/10.1109/CANDAR.2019.00016","url":null,"abstract":"Hybrid storage techniques are useful methods to improve the cost performance for input-output (IO) intensive workloads. These techniques choose areas of concentrated IO accesses and migrate them to an upper tier to extract as much performance as possible through greater use of upper tier areas. Automated tiered storage with fast memory and slow flash storage (ATSMF) is a hybrid storage system situated between non-volatile memories (NVMs) and solid-state drives (SSDs). ATSMF aims to reduce the average response time for IO accesses by migrating areas of concentrated IO access from an SSD to an NVM. When a concentrated IO access finishes, the system migrates these areas from the NVM back to the SSD. Unfortunately, the published ATSMF implementation temporarily consumes much NVM capacity upon migrating concentrated IO access areas to NVM, because its algorithm executes NVM migration with high priority. As a result, it often delays evicting areas in which IO concentrations have ended to the SSD. Therefore, to reduce the consumption of NVM while maintaining the average response time, we developed new techniques for making ATSMF more practical. The first is a queue handling technique based on the number of IO accesses for NVM migration and eviction. The second is an eviction method that selects only write-accessed partial regions in finished areas. The third is a technique for variable eviction timing to balance the NVM consumption and average response time. Experimental results indicate that the average response times of the proposed ATSMF are almost the same as those of the published ATSMF, while the NVM consumption is drastically lower.","PeriodicalId":300306,"journal":{"name":"2019 Seventh International Symposium on Computing and Networking (CANDAR)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122003141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation 基于fpga的量子退火模拟无数据传输瓶颈架构

2019 Seventh International Symposium on Computing and Networking (CANDAR) Pub Date : 2019-11-01 DOI: 10.1109/CANDAR.2019.00028

Chia-Yin Liu, H. M. Waidyasooriya, M. Hariyama

{"title":"Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation","authors":"Chia-Yin Liu, H. M. Waidyasooriya, M. Hariyama","doi":"10.1109/CANDAR.2019.00028","DOIUrl":"https://doi.org/10.1109/CANDAR.2019.00028","url":null,"abstract":"Quantum Annealing (QA) is a classical probabilistic algorithm that provides a heuristic to find the globally optimal solution for a combinatorial optimization problem by using quantum tunneling processes. Quantum annealing simulation can be implemented on Field Programmable Gate Arrays (FPGAs) using Quantum Monte Carlo (QMC) simulation in the transverse Ising model. Since input data of the QMC simulation increases exponentially with the problem size, we have to use the DRAM of an FPGA board to store these data. However, storing data in DRAM causes two problems. One is the limited data access bandwidth, and the other is the limitation of DRAM capacity. We propose a data-transfer-bottleneck-less FPGA-based accelerator for quantum annealing simulation and apply it to implement number partitioning problem, which is one of the combinatorial optimization problems. The critical idea of our architecture is not storing but computing the large data in FPGA kernels and eliminating the burden on data transfer. We implement the proposed architecture on Stratix 10 FPGA and achieve up to 39.6 times speed-up compared to CPU-based quantum annealing simulation. We also achieve up to 2.8 times speed-up and implement 262,144 spins, which is 64 times increase compared to the most recent FPGA implementation.","PeriodicalId":300306,"journal":{"name":"2019 Seventh International Symposium on Computing and Networking (CANDAR)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122282844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Siva - The IPFS Search Engine Siva - IPFS搜索引擎

2019 Seventh International Symposium on Computing and Networking (CANDAR) Pub Date : 2019-07-08 DOI: 10.1109/CANDAR.2019.00026

Nawras Khudhur, S. Fujita

引用次数: 8