发布求助
文献互助 智能选刊 最新文献

VLSI Signal Processing, VIII最新文献

筛选
英文 中文
Information based design environment 基于信息的设计环境
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527495
O. Bentz, D. Lidsky, J. Rabaey
{"title":"Information based design environment","authors":"O. Bentz, D. Lidsky, J. Rabaey","doi":"10.1109/VLSISP.1995.527495","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527495","url":null,"abstract":"An information based system design environment is presented. The environment is information based because it helps users collect and manage information in a uniform fashion, independent of abstraction levels or implementation platforms. The environment is particularly aimed at providing feedback, design guidance, and support for design exploration. The concepts are demonstrated in a prototype called the \"Design Agent\".","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An ASIC implementation of range cell migration compensation algorithm for synthetic aperture radar signal processing 合成孔径雷达信号处理中距离元偏移补偿算法的ASIC实现
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527485
J. Dongun Kim, L. Kim
{"title":"An ASIC implementation of range cell migration compensation algorithm for synthetic aperture radar signal processing","authors":"J. Dongun Kim, L. Kim","doi":"10.1109/VLSISP.1995.527485","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527485","url":null,"abstract":"Nonlinear range curvature effect and linear range walk effect appearing in collected SAR data array cause SAR image quality to be distorted. Therefore, two kinds of range cell migration (RCM) compensation processing are required in addition to the two dimensional pulse compression processes. In this paper, special purpose hardware which compensates for these linear and nonlinear cell migration effects are implemented in architecture level and logic level by using the compensation algorithm used in digital SAR processing. Pre-layout simulations using CAD tools are also carried out to verify the normal operation of the designed hardware. SAR parameters used during compensation processing are the parameters for spaceborne SEASAT SAR launched in 1978. Data block to be processed is composed of 4096 pulses/spl times/4096 samples.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Architectural considerations in a configurable DSP core for consumer electronics 消费类电子产品中可配置DSP核心的架构考虑
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527478
H. Yagi, R. Owen
{"title":"Architectural considerations in a configurable DSP core for consumer electronics","authors":"H. Yagi, R. Owen","doi":"10.1109/VLSISP.1995.527478","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527478","url":null,"abstract":"This paper reviews the design methodology used to develop a new system of configurable modules for DSP in consumer electronics. To meet the various needs of low-cost consumer products required a configurable hardware architecture and a new form of instruction set to support it. The CD2450 has such an extendable architecture and instruction set. It is described and results are given on what has produced the best cost-performance designs.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123623118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Probabilistic resource estimation for pipeline architecture 管道结构的概率资源估计
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527493
J. Diguet, O. Sentieys, J. Philippe, E. Martin
{"title":"Probabilistic resource estimation for pipeline architecture","authors":"J. Diguet, O. Sentieys, J. Philippe, E. Martin","doi":"10.1109/VLSISP.1995.527493","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527493","url":null,"abstract":"This paper presents a new approach to resource estimation in high level synthesis. Given a set of operators and a data flow graph specification, we apply a probability based method to compute the probable numbers of operators, registers, bus and operator connections for each time step or algorithm latency. Combined with statistical metrics, we obtain a quick and accurate estimation module that includes real precedence constraints. The aim of this work is to provide ASICs designers with a guidance tool for a better use of high level synthesis. Algorithm properties like dated resource concurrence and operator link statistics are computed to guide algorithmic, transformations and hardware selection.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129162215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Image sensor for compression and enhancement 用于压缩和增强的图像传感器
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527477
T. Hamamoto, K. Aizawa, Y. Egi, M. Hatori, J. Yamazaki
{"title":"Image sensor for compression and enhancement","authors":"T. Hamamoto, K. Aizawa, Y. Egi, M. Hatori, J. Yamazaki","doi":"10.1109/VLSISP.1995.527477","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527477","url":null,"abstract":"In this paper, we propose a novel image sensor on which a video signal can be compressed. By making use of very fast analog processing on the imager plane, the compression sensor can significantly reduce the amount of pixel data output from the sensor. A prototype sensor with 32/spl times/32 pixels has been fabricated using standard 2 /spl mu/m CMOS technology. Some results of examinations are shown in this paper. We also describe a motion adaptive enhancement sensor which controls storage time independently pixel by pixel. The proposed sensor is intended to have high temporal resolution in the moving area and high SNR in the static area. According to preliminary experiments, the value of SNR increases about 5 dB compared to the video compression sensor.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127708949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A systolic array for sliding window constrained RLS 一种用于滑动窗口约束RLS的收缩阵列
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527504
H. Sakai, M. Kuroda
{"title":"A systolic array for sliding window constrained RLS","authors":"H. Sakai, M. Kuroda","doi":"10.1109/VLSISP.1995.527504","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527504","url":null,"abstract":"An algorithm is derived for extracting tap coefficients of sliding window constrained RLS based on QR decomposition and its systolic array implementation is presented.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI chip design of a CORDIC-based adaptive lattice filter VLSI芯片设计了一种基于cordic的自适应点阵滤波器
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527508
Jeng-Kuang Hwang, Jing-Hsien Chang
{"title":"VLSI chip design of a CORDIC-based adaptive lattice filter","authors":"Jeng-Kuang Hwang, Jing-Hsien Chang","doi":"10.1109/VLSISP.1995.527508","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527508","url":null,"abstract":"This work describes a 16-bit fixed-point VLSI chip design of an adaptive lattice filter (ELF) which is suitable for linear prediction or AR modeling with a filter order up to sixteen. The adaptation algorithm is based on the Burg algorithm, and the chip design employs the CORDIC arithmetic. The chip can operate in three modes. With the multi-stage single chip mode, the lattice filtering and adaptation operations are done recursively each time a new input data arrives. With the multi-stage multi-chip mode, cascading multiple identical chips can extend the filter to a higher desired order. With the single-stage multi-chip mode, L chips can be connected as a pipeline to form a L-stage lattice filter with each chip serving as one lattice stage. This mode can achieve a highest filtering speed of 1.7 M samples/sec. Besides, in implementing the Burg algorithm, a practical computing scheme is used such as to avoid internal overflow and improve the numerical accuracy.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126690406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Memory management in high-speed Viterbi decoders 高速维特比解码器的内存管理
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527522
Minjoong Rim, Young-Uk Oh
{"title":"Memory management in high-speed Viterbi decoders","authors":"Minjoong Rim, Young-Uk Oh","doi":"10.1109/VLSISP.1995.527522","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527522","url":null,"abstract":"Memory management is one of the most important problems in implementing Viterbi decoders. This paper introduces a novel traceback scheme for memory management of high-speed Viterbi decoders. It is suitable for VLSI implementation since its address generation scheme for accessing memory contents is very simple and does not require global interconnection.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134350934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low-power encoder architecture for pyramid vector quantization of 2D subband coefficients 二维子带系数金字塔矢量量化的低功耗编码器结构
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527510
W. Namgoong, M. Devenport, T. Meng
{"title":"A low-power encoder architecture for pyramid vector quantization of 2D subband coefficients","authors":"W. Namgoong, M. Devenport, T. Meng","doi":"10.1109/VLSISP.1995.527510","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527510","url":null,"abstract":"This paper describes a VLSI architecture designed to pyramid vector quantize (PVQ) 2-D subband image for low-power portable applications. Using the 0.8 /spl mu/ CMOS process, the chip is estimated to dissipate less than 300 /spl mu/W at a 1.5 V supply, encoding at 1.27 Mpixels/sec, for display of 240 pixels wide, 176 lines, and 30 frames per second, while introducing no noticeable degradation in the decompressed video quality. Low power consumption is achieved through efficient algorithm-to-hardware mapping requiring no multipliers, dividers, or external memory accesses, innovative computational methods, and reduction in supply voltage.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134220448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Systematic design of architectures for M-ary tree-structured filter banks m树结构滤波器组体系结构的系统设计
VLSI Signal Processing, VIII Pub Date : 1995-10-16 DOI: 10.1109/VLSISP.1995.527487
T. C. Denk, K. Parhi
{"title":"Systematic design of architectures for M-ary tree-structured filter banks","authors":"T. C. Denk, K. Parhi","doi":"10.1109/VLSISP.1995.527487","DOIUrl":"https://doi.org/10.1109/VLSISP.1995.527487","url":null,"abstract":"This paper presents an approach for systematically synthesizing VLSI architectures for M-ary tree-structured filter banks which are constructed from a prototype M-channel FIR filter bank. The resulting synchronous architecture is single-rate, i.e., the architecture uses a single clock even though it implements a multirate algorithm. We derive folding equations and use retiming for folding multirate systems to synthesize the control circuitry. A scheduling algorithm is presented which retimes the multirate filter bank to keep the memory requirements of the architecture low. Our approach can be used to design architectures for a wide variety of applications of full and pruned tree-structured filter banks including subband decompositions, discrete wavelet transforms, and computation of wavelet packet bases.","PeriodicalId":286121,"journal":{"name":"VLSI Signal Processing, VIII","volume":"180 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132478685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信