B. Mills, Ryan E. Grant, Kurt B. Ferreira, R. Riesen
{"title":"Evaluating energy savings for checkpoint/restart","authors":"B. Mills, Ryan E. Grant, Kurt B. Ferreira, R. Riesen","doi":"10.1145/2536430.2536432","DOIUrl":"https://doi.org/10.1145/2536430.2536432","url":null,"abstract":"The U. S. Department of Energy has identified resilience and energy consumption as key challenges for future extreme-scale systems. All checkpoint/restart methods require I/O to local or remote storage. Efforts are under way to minimize the amount of data movement and increase scalability. Nevertheless, the energy consumed by fault resilience methods will increase with system size. It is therefore important to understand the performance overhead in conjunction with the energy consumption of each fault resilience method. In this paper we explore throttling CPU power consumption during I/O intensive checkpoint operations of real applications. We find that 10% total energy savings are possible with little impact on application time to solution.","PeriodicalId":285336,"journal":{"name":"International Workshop on Energy Efficient Supercomputing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126917054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Allan Porterfield, R. Fowler, Sridutt Bhalachandra, Wei Wang
{"title":"OpenMP and MPI application energy measurement variation","authors":"Allan Porterfield, R. Fowler, Sridutt Bhalachandra, Wei Wang","doi":"10.1145/2536430.2536437","DOIUrl":"https://doi.org/10.1145/2536430.2536437","url":null,"abstract":"Power, energy, and compute time are all important metrics that can act as either objectives or constraints in program or system optimization. Recent microprocessors include sensors (counters) for monitoring these metrics as well as on-chip system controllers that may use this information. Code optimization is relatively straightforward if the measurements are stable and repeatable over time on nominally identical hardware, if there is a lot of variance it becomes very difficult. This paper describes experiments that expose the variability of performance and energy usage on recent Intel processors for some parallel benchmarks using shared memory (OpenMP) and message passing (MPI) programming models. During the start up phase going from a quiescent to a \"hot\" steady state temperature differences of greater than 26°C were seen resulting in run-to-run energy differences as large as 10%. Even in steady state, run-to-run variability in execution time and energy usage were problematic. The patterns of variability found in execution time and energy consumption pose a challenge to simple strategies for running performance experiments as part of a tuning framework.","PeriodicalId":285336,"journal":{"name":"International Workshop on Energy Efficient Supercomputing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121572298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling the effects of DFS on power consumption in hybrid chip multiprocessors","authors":"A. Marowka","doi":"10.1145/2536430.2536436","DOIUrl":"https://doi.org/10.1145/2536430.2536436","url":null,"abstract":"The power wall is one of the primary stumbling blocks that many-core microprocessor architecture is facing today. To avoid this problem, microprocessor makers are shifting towards heterogeneous chips that integrate different core architectures on a single die and that have proved to deliver better performance per watt. Moreover, these new hybrid microprocessors are equipped with dynamic frequency-scaling techniques that are capable of reducing total system power consumption.\u0000 This paper presents a theoretical study on how performance and power consumption are affected by the dynamic frequency-scaling techniques offered by the power constraints imposed on state-of-the-art dual-architecture processors. Analytical schemes have been developed to extend Amdahl's Law by accounting for energy limitations before examining the three processing schemes available to heterogeneous processors: symmetric, asymmetric, and simultaneous asymmetric. Analysis shows that by choosing the optimal chip configuration, power efficiency and energy savings can be increased considerably while keeping sacrifices in performance at tolerable levels.","PeriodicalId":285336,"journal":{"name":"International Workshop on Energy Efficient Supercomputing","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133713957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Initial investigation of a scheme to use instantaneous CPU power consumption for energy savings format","authors":"Vaibhav Sundriyal, M. Sosonkina","doi":"10.1145/2536430.2536433","DOIUrl":"https://doi.org/10.1145/2536430.2536433","url":null,"abstract":"The drive to extract peak performance from the modern computing platforms has lead to drastic increase in their energy and power consumption and thereby affecting the operating costs and failure rates. Modern processors provide techniques, such as dynamic voltage and frequency scaling (DVFS) and CPU clock modulation (called throttling), to improve energy efficiency on-the-fly. Without careful application, however, DVFS and throttling may cause a significant performance loss due to the system overhead. Much research attempts to use these techniques by choosing a performance loss for the application, under which the energy savings are to be obtained. This paper discusses potential pitfalls of the performance-loss approach and proposes a frequency scaling scheme that is based on instantaneous CPU power consumption, and thus, avoids the need for the user to predefine performance tolerance. Preliminary experiments, performed on NAS benchmarks, show that the proposed scheme saves more energy than the approach based on the predefined performance loss.","PeriodicalId":285336,"journal":{"name":"International Workshop on Energy Efficient Supercomputing","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131013238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}