ASPLOS VII最新文献_第2页

Multiple-block ahead branch predictors 多块超前分支预测器

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237169

André Seznec, S. Jourdan, P. Sainrat, P. Michaud

引用次数: 115

Operating system support for improving data locality on CC-NUMA compute servers 操作系统支持改进CC-NUMA计算服务器上的数据局部性

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237205

Ben Verghese, Scott Devine, Anoop Gupta, M. Rosenblum

{"title":"Operating system support for improving data locality on CC-NUMA compute servers","authors":"Ben Verghese, Scott Devine, Anoop Gupta, M. Rosenblum","doi":"10.1145/237090.237205","DOIUrl":"https://doi.org/10.1145/237090.237205","url":null,"abstract":"The dominant architecture for the next generation of shared-memory multiprocessors is CC-NUMA (cache-coherent non-uniform memory architecture). These machines are attractive as compute servers because they provide transparent access to local and remote memory. However, the access latency to remote memory is 3 to 5 times the latency to local memory. CC-NOW machines provide the benefits of cache coherence to networks of workstations, at the cost of even higher remote access latency. Given the large remote access latencies of these architectures, data locality is potentially the most important performance issue. Using realistic workloads, we study the performance improvements provided by OS supported dynamic page migration and replication. Analyzing our kernel-based implementation, we provide a detailed breakdown of the costs. We show that sampling of cache misses can be used to reduce cost without compromising performance, and that TLB misses may not be a consistent approximation for cache misses. Finally, our experiments show that dynamic page migration and replication can substantially increase application performance, as much as 30%, and reduce contention for resources in the NUMA memory system.","PeriodicalId":281325,"journal":{"name":"ASPLOS VII","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130854324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 275

SoftFLASH: analyzing the performance of clustered distributed virtual shared memory SoftFLASH:集群分布式虚拟共享内存性能分析

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237187

Andrew Erlichson, Neal Nuckolls, G. Chesson, J. Hennessy

{"title":"SoftFLASH: analyzing the performance of clustered distributed virtual shared memory","authors":"Andrew Erlichson, Neal Nuckolls, G. Chesson, J. Hennessy","doi":"10.1145/237090.237187","DOIUrl":"https://doi.org/10.1145/237090.237187","url":null,"abstract":"One potentially attractive way to build large-scale shared-memory machines is to use small-scale to medium-scale shared-memory machines as clusters that are interconnected with an off-the-shelf network. To create a shared-memory programming environment across the clusters, it is possible to use a virtual shared-memory software layer. Because of the low latency and high bandwidth of the interconnect available within each cluster, there are clear advantages in making the clusters as large as possible. The critical question then becomes whether the latency and bandwidth of the top-level network and the software system are sufficient to support the communication demands generated by the clusters.To explore these questions, we have built an aggressive kernel implementation of a virtual shared-memory system using SGI multiprocessors and 100Mbyte/sec HIPPI interconnects. The system obtains speedups on 32 processors (four nodes, eight processors per node plus additional reserved protocol processors) that range from 6.9 on the communication-intensive FFT program to 21.6 on Ocean (both from the SPLASH 2 suite). In general, clustering is effective in reducing internode miss rates, but as the cluster size increases, increases in the remote latency, mostly due to increased TLB synchronization cost, offset the advantages. For communication-intensive applications, such as FFT, the overhead of sending out network requests, the limited network bandwidth, and the long network latency prevent the achievement of good performance. Overall, this approach still appears promising, but our results indicate that large low latency networks may be needed to make cluster-based virtual shared-memory machines broadly useful as large-scale shared-memory multiprocessors.","PeriodicalId":281325,"journal":{"name":"ASPLOS VII","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 109

Improving cache performance with balanced tag and data paths 通过平衡标签和数据路径提高缓存性能

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237202

J. Peir, W. Hsu, H. Young, S. Ong

引用次数: 14

Hiding communication latency and coherence overhead in software DSMs 在软件dsm中隐藏通信延迟和一致性开销

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237185

R. Bianchini, L. Kontothanassis, R. Pinto, M. D. Maria, M. Abud, C. Amorim

{"title":"Hiding communication latency and coherence overhead in software DSMs","authors":"R. Bianchini, L. Kontothanassis, R. Pinto, M. D. Maria, M. Abud, C. Amorim","doi":"10.1145/237090.237185","DOIUrl":"https://doi.org/10.1145/237090.237185","url":null,"abstract":"In this paper we propose the use of a PCI-based programmable protocol controller for hiding communication and coherence overheads in software DSMs. Our protocol controller provides three different types of overhead tolerance: a) moving basic communication and coherence tasks away from computation processors; b) prefetching of diffs; and c) generating and applying diffs with hardware assistance. We evaluate the isolated and combined impact of these features on the performance of TreadMarks. We also compare performance against two versions of the Shrimp-based AURC protocol. Using detailed execution-driven simulations of a 16-node network of workstations, we show that the greatest performance benefits provided by our protocol controller come from our hardware-supported diffs. Reducing the burden of communication and coherence transactions on the computation processor is also beneficial but to a smaller extent. Prefetching is not always profitable. Our results show that our protocol controller can improve running time performance by up to 50% for TreadMarks, which means that it can double the TreadMarks speedups. The overlapping implementation of TreadMarks performs as well or better than AURC for 5 of our 6 applications. We conclude that the simple hardware support we propose allows for the implementation of high-performance software DSMs at low cost. Based on this conclusion, we are building the NCP2 parallel system at COPPE/UFRJ.","PeriodicalId":281325,"journal":{"name":"ASPLOS VII","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 70

Thread scheduling for cache locality 缓存局部性的线程调度

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237151

J. Philbin, J. Edler, Otto J. Anshus, C. Douglas, Kai Li

引用次数: 100

An evaluation of memory consistency models for shared-memory systems with ILP processors 具有ILP处理器的共享内存系统的内存一致性模型的评估

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237142

Vijay S. Pai, Parthasarathy Ranganathan, S. Adve, Tracy Harton

{"title":"An evaluation of memory consistency models for shared-memory systems with ILP processors","authors":"Vijay S. Pai, Parthasarathy Ranganathan, S. Adve, Tracy Harton","doi":"10.1145/237090.237142","DOIUrl":"https://doi.org/10.1145/237090.237142","url":null,"abstract":"Relaxed consistency models have been shown to significantly outperform sequential consistency for single-issue, statically scheduled processors with blocking reads. However, current microprocessors aggressively exploit instruction-level parallelism (ILP) using methods such as multiple issue, dynamic scheduling, and non-blocking reads. Researchers have conjectured that two techniques, hardware-controlled non-binding prefetching and speculative loads, have the potential to equalize the hardware performance of memory consistency models on such processors.This paper performs the first detailed quantitative comparison of several implementations of sequential consistency and release consistency optimized for aggressive ILP processors. Our results indicate that hardware prefetching and speculative loads dramatically improve the performance of sequential consistency. However, the gap between sequential consistency and release consistency depends on the cache write policy and the complexity of the cache-coherence protocol implementation. In most cases, release consistency significantly outperforms sequential consistency, but for two applications, the use of a write-back primary cache and a more complex cache-coherence protocol nearly equalizes the performance of the two models.We also observe that the existing techniques, which require on-chip hardware modifications, enhance the performance of release consistency only to a small extent. We propose two new software techniques --- fuzzy acquires and selective acquires --- to achieve more overlap than allowed by the previous implementations of release consistency. To enhance methods for overlapping acquires, we also propose a technique to eliminate control dependences caused by an acquire loop, using a small amount of off-chip hardware called the synchronization buffer.","PeriodicalId":281325,"journal":{"name":"ASPLOS VII","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115939557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 76

The case for a single-chip multiprocessor 单芯片多处理器的案例

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237140

K. Olukotun, B. A. Nayfeh, Lance Hammond, Kenneth G. Wilson, Kunyung Chang

引用次数: 865

The intrinsic bandwidth requirements of ordinary programs 普通程序的固有带宽要求

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237163

A. Huang, John Paul Shen

{"title":"The intrinsic bandwidth requirements of ordinary programs","authors":"A. Huang, John Paul Shen","doi":"10.1145/237090.237163","DOIUrl":"https://doi.org/10.1145/237090.237163","url":null,"abstract":"While there has been an abundance of recent papers on hardware and software approaches to improving the performance of memory accesses, few papers have addressed the problem from the program's point of view. There is a general notion that certain programs have larger working sets than others. However, there is no quantitative method for evaluating and comparing the memory requirements of programs.This paper introduces the bandwidth spectrum for characterizing the memory requirements of a program's instruction and data stream. The bandwidth spectrum measures the average bandwidth requirement of a program as a function of available local memory. These measurements are performed under the most idealized conditions of perfect knowledge and perfect memory management. As such, they represent the lower bounds on the memory requirements of programs. We present the bandwidth spectrums for a set of 22 benchmarks and show how they can be used in the comparison of memory requirements and I/O requirement. The bandwidth spectrums also offer a convenient method to weigh the trade-off amongst instruction issue rate, local memory capacity and bandwidth into local memory.Using the bandwidth spectrum, we show that at issue rates of four or less, bandwidth usually scales linearly with the issue rate. At higher issue rates, bandwidth can often scale superlinearly with respect to issue rate. Finally, we also investigate the effects of varying the input sets on the bandwidth spectrums.","PeriodicalId":281325,"journal":{"name":"ASPLOS VII","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122329753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Reducing network latency using subpages in a global memory environment 在全局内存环境中使用子页面减少网络延迟

ASPLOS VII Pub Date : 1996-10-01 DOI: 10.1145/237090.237198

H. Jamrozik, M. Feeley, G. Voelker, J. Evans, Anna R. Karlin, H. Levy, M. Vernon

{"title":"Reducing network latency using subpages in a global memory environment","authors":"H. Jamrozik, M. Feeley, G. Voelker, J. Evans, Anna R. Karlin, H. Levy, M. Vernon","doi":"10.1145/237090.237198","DOIUrl":"https://doi.org/10.1145/237090.237198","url":null,"abstract":"New high-speed networks greatly encourage the use of network memory as a cache for virtual memory and file pages, thereby reducing the need for disk access. Because pages are the fundamental transfer and access units in remote memory systems, page size is a key performance factor. Recently, page sizes of modern processors have been increasing in order to provide more TLB coverage and amortize disk access costs. Unfortunately, for high-speed networks, small transfers are needed to provide low latency. This trend in page size is thus at odds with the use of network memory on high-speed networks.This paper studies the use of subpages as a means of reducing transfer size and latency in a remote-memory environment. Using trace-driven simulation, we show how and why subpages reduce latency and improve performance of programs using network memory. Our results show that memory-intensive applications execute up to 1.8 times faster when executing with 1K-byte subpages, when compared to the same applications using full 8K-byte pages in the global memory system. Those same applications using 1K-byte subpages execute up to 4 times faster than they would using the disk for backing store. Using a prototype implementation on the DEC Alpha and AN2 network, we demonstrate how subpages can reduce remote-memory fault time; e.g., our prototype is able to satisfy a fault on a 1K subpage stored in remote memory in 0.5 milliseconds, one third the time of a full page.","PeriodicalId":281325,"journal":{"name":"ASPLOS VII","volume":"76 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128283534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37