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2008 International Conference on Embedded Software and Systems最新文献

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Routing in Multi-Sink Sensor Networks Based on Gravitational Field 基于重力场的多汇聚传感器网络路由
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.14
Jinbao Li, S. Ji, Hu Jin, Qianqian Ren
{"title":"Routing in Multi-Sink Sensor Networks Based on Gravitational Field","authors":"Jinbao Li, S. Ji, Hu Jin, Qianqian Ren","doi":"10.1109/ICESS.2008.14","DOIUrl":"https://doi.org/10.1109/ICESS.2008.14","url":null,"abstract":"The process of data forwarding in sensor networks is analogy to electric charge moving in electrostatic field. By this analogy, a method which abstracting a sensor networks to a Gravitational Field is proposed in this paper. In this gravitational field, sink node has gravitational to the data and data can flow to sink under this gravitational. Based on this gravitational field, a routing method which applies well in Multi-Sink sensor networks is proposed in this paper. This method has a lower time and space complexity, and it can adapt to the variety of the networks size dynamically. Theoretic analysis and simulation results indicate that: the routing method this paper proposed can decrease the energy consuming of data transmission effectively, reduce the data packet discard rate, uniform the networks' loads, and prolong the lifecycle of the networks.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134232178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Chaotic Routing: A Set-based Broadcasting Routing Framework for Wireless Sensor Networks 混沌路由:一种基于集的无线传感器网络广播路由框架
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.70
Haiyang Liu, S. Kolavennu
{"title":"Chaotic Routing: A Set-based Broadcasting Routing Framework for Wireless Sensor Networks","authors":"Haiyang Liu, S. Kolavennu","doi":"10.1109/ICESS.2008.70","DOIUrl":"https://doi.org/10.1109/ICESS.2008.70","url":null,"abstract":"Data communication in wireless sensor networks (WSNs) exhibits distinctive characteristics. Routing in WSNs still relies on simple variations of traditional distance vector or link state based protocols, thus suffering low throughput and less robustness. Drawing intuitions from the Brownian motions where localized momentum exchanges enable global energy diffusion, we propose an innovative routing protocol, chaotic routing (CR), which achieves efficient information diffusion with seemingly chaotic local information exchanges. Leveraging emerging networking concepts such as potential based routing, opportunistic routing and network coding, CR improves throughput via accurate routing cost estimation, opportunistic data forwarding and localized node scheduling optimizing information propagation in mesh structures. Through extensive simulations, we prove that CR outperforms, in terms of throughput, best deterministic routing scheme (i.e. best path routing) by a factor of around 300% and beats the best opportunistic routing scheme (i.e. MORE) by a factor of around 200%. CR shows stable performance over wide range of network densities, link qualities and batch sizes.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123250755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel high-capability control-flow checking technique for RISC architectures 一种面向RISC体系结构的高性能控制流检测技术
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.77
Jianghong Huang, Yuxiang Li, Lisheng Zhang, Yingke Xie, Chengde Han
{"title":"A novel high-capability control-flow checking technique for RISC architectures","authors":"Jianghong Huang, Yuxiang Li, Lisheng Zhang, Yingke Xie, Chengde Han","doi":"10.1109/ICESS.2008.77","DOIUrl":"https://doi.org/10.1109/ICESS.2008.77","url":null,"abstract":"Nowadays more and more small transistors make microprocessors more susceptible to transient faults, and then induce control-flow errors. Software-based signature monitoring is widely used for control-flow error detection. When previous signature monitoring techniques are applied to RISC architectures, there exist some branch-errors that they can not detect. This paper proposes a novel software-based signature monitoring technique: CFC-End (Control-Flow Checking in the End). One property of CFC-End is that it uses two global registers for storing the run-time signature alternately. Another property of CFC-End is that it compares the run-time signature with the assigned signature in the end of every basic block. CFC-End is better than previous techniques in the sense that it can detect any single branch-error when applied to RISC architectures. CFC-End has similar performance overhead in comparison with the RCF (Region based Control-Flow checking) technique, which has the highest capability of branch-error detection among previous techniques.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116838698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient H.264 Architecture Using Modular Bandwidth Estimation 采用模块化带宽估计的高效H.264架构
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.27
Ruei-Xi Chen, Wei Zhao, Qinyi Liu, Jeffrey Fan
{"title":"Efficient H.264 Architecture Using Modular Bandwidth Estimation","authors":"Ruei-Xi Chen, Wei Zhao, Qinyi Liu, Jeffrey Fan","doi":"10.1109/ICESS.2008.27","DOIUrl":"https://doi.org/10.1109/ICESS.2008.27","url":null,"abstract":"Bandwidth is always one of the bottlenecks in system-on-a-chip (SoC) systems. In this paper, we propose an efficient architectural design in analyzing the bandwidth of each component in an H.264 design. We decompose the entire H.264 system bandwidths into several modules with predictable coefficients. The derived equations may help designers understand the real cost of each hardware component, thus improving the efficiency of overall system. The main idea of this paper is to generate an H.264 architecture with all the desired features possible. If the model is unable to fit well in the overall system or subsystem, the designer can detect and modify the architecture in the early stage of the product development cycle, thus reducing the potential risk of system re-design.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129365267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Intrusion Aware System-on-a-Chip Design with Uncertainty Classification 基于不确定性分类的入侵感知片上系统设计
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.28
T. Chou, Sharon Fan, Wei Zhao, Jeffrey Fan, A. Davari
{"title":"Intrusion Aware System-on-a-Chip Design with Uncertainty Classification","authors":"T. Chou, Sharon Fan, Wei Zhao, Jeffrey Fan, A. Davari","doi":"10.1109/ICESS.2008.28","DOIUrl":"https://doi.org/10.1109/ICESS.2008.28","url":null,"abstract":"In this paper, we have proposed a System-on-a-Chip (SoC) architectural design to avoid potential intrusion or attacks from external devices. Either using misuse detection or anomaly detection techniques to design intrusion detection systems, a large amount of traffic data is needed to be collected in advance for analysis. However, it is not feasible in the limited resources available in SoC systems. We propose to incorporate fuzzy clustering technique along with Dempster-Shafer theory into our intrusion detection design to solve uncertainty problems caused by ambiguous and limited information. Also, the k-NN technique is applied to speed up the detection process. We compare the results of our proposed approach with those of k-NN classifier, fuzzy k-NN classifier and evidence-theoretic k-NN classifier. It indicates that our approach is able to achieve higher detection rates than those from the other three classifiers, thus is more useful in the implementation of intrusion aware mechanism in SoC design.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Energy-Balanced Relaying Communication Protocol Based on Power and Distance Cooperation 基于功率与距离协同的能量平衡中继通信协议
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.32
Shaoyan Huang, Jianping Xing, Dejing Zhang, Xiling Luo, Jun Zhang
{"title":"An Energy-Balanced Relaying Communication Protocol Based on Power and Distance Cooperation","authors":"Shaoyan Huang, Jianping Xing, Dejing Zhang, Xiling Luo, Jun Zhang","doi":"10.1109/ICESS.2008.32","DOIUrl":"https://doi.org/10.1109/ICESS.2008.32","url":null,"abstract":"Wireless sensor networks (WSNs) composed of a large number of cheap microsensor nodes with limited battery power and highly correlated collected data is intelligent and autonomous system for measure and management. To reduce the redundant data among the nodes and consequently prolong networkspsila lifetime, clustering protocols which perform application-specific local data aggregation have been put forward. To balance energy consumption in the whole network, in this paper, we propose and analyze energy-balanced adaptive clustering hierarchy (EBACH) protocol, a novel approach adding a new kind node called relay-node besides cluster-head and cluster member node. Simulation results demonstrate that our energy balancing mechanism can obviously improve the system performance compared with general clustering protocols.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122444076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Multiple Background Images Model for Billet Location Control 基于多背景图像的钢坯定位控制模型
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.69
Xiaoyu Liu, Kang-ling Fang
{"title":"A Multiple Background Images Model for Billet Location Control","authors":"Xiaoyu Liu, Kang-ling Fang","doi":"10.1109/ICESS.2008.69","DOIUrl":"https://doi.org/10.1109/ICESS.2008.69","url":null,"abstract":"This paper addresses the problem of real-time location of billet in the heating kiln of a steel mill, and presents a vision-based steel billet location control system. The locations of the billets are obtained by background subtraction method. The major difficulty is the strong illumination changes in the heating kiln with the temperature changes. This paper adopts the idea of multiple background images model to adapt the illumination changes in the heating kiln. The multiple background images model classifies the background images as three representative background images, and provides an adaptive weight mechanism for switching a background image among three representative background images. The practical experimental result shows the algorithm is effective and fast, and can meet the demand of real-time control. The vision-based location control system has been successfully used to track the billet edge in industrial condition, and can obtain good control performances under the industrial environment.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Electronic System Level Design and Performance Evaluation for Multimedia Applications 面向多媒体应用的电子系统级设计与性能评估
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.94
T. Tsai, Yu-Nan Pan, Chia-Hung Lin
{"title":"An Electronic System Level Design and Performance Evaluation for Multimedia Applications","authors":"T. Tsai, Yu-Nan Pan, Chia-Hung Lin","doi":"10.1109/ICESS.2008.94","DOIUrl":"https://doi.org/10.1109/ICESS.2008.94","url":null,"abstract":"With complexities of systems-on-chips (SoCs) rising almost daily, the system designers have been searching for new design methodology that can handle given complexities with decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However the system designers also care about the system architectures, HW/SW performance, and communication protocols. Furthermore, the transaction-level model (TLM) can satisfy the requests on complex design with relative high simulation speed and well performance evaluation. In this paper, we implement a TLM-based network-on-chip (NoC) platform and share-bus system architecture with SystemC. We also implement the H.263 encoder as the system application, and apply a design methodology at electronic-system level (ESL) to make design modeling, design space exploration and performance evaluation. Out platform is able to evaluate performance in relatively short time, obtain important information and complete the design more instinctively. In addition, we compare and contrast the NoC and share-bus system architectures in terms of evaluation performance. In experimental result, the performance bottleneck in communication congestion is solved well by using the NoC instead of using the share-bus design.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127517484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Energy Efficient Real-Time DVS based on Genetic Algorithm 基于遗传算法的节能实时分布式交换机
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.84
J. Xun, Huayong Wang, Wu Nian, Wu Dexin, Wang Jian Fen
{"title":"Energy Efficient Real-Time DVS based on Genetic Algorithm","authors":"J. Xun, Huayong Wang, Wu Nian, Wu Dexin, Wang Jian Fen","doi":"10.1109/ICESS.2008.84","DOIUrl":"https://doi.org/10.1109/ICESS.2008.84","url":null,"abstract":"This paper proposes a novel real-time dynamic voltage scheduling algorithm(GA-DVS) based on genetic algorithm for periodically real-time task set. Based on a mathematical system model in the real situation, the GA-DVS algorithm is different from classical DVS algorithms, some critical parts of which are specially designed, such as encoding, the fitness function, the crossover/mutation/repair operator and the termination condition; GA-DVS searches from multiple initial points, mutates during the search process and uses the repair operator to guarantee the convergence of the algorithm. GA-DVS can give optimal solution for the hard real-time task on CPUs with N adjustable frequencies and voltages in most cases. Finally, experimental results demonstrate the efficiency of the GA-DVS algorithm, which can achieve a good tradeoff between time cost and precision and search effectively in the solution space of the NP-complete problem.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132834513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
HW/SW Auto-Coupling for Fast IP Integration in SoC Designs 硬件/软件自动耦合用于SoC设计中的快速IP集成
2008 International Conference on Embedded Software and Systems Pub Date : 2008-07-29 DOI: 10.1109/ICESS.2008.91
Y. Hwang, Jun-Yen Chen, Jun-Jieh Chiu
{"title":"HW/SW Auto-Coupling for Fast IP Integration in SoC Designs","authors":"Y. Hwang, Jun-Yen Chen, Jun-Jieh Chiu","doi":"10.1109/ICESS.2008.91","DOIUrl":"https://doi.org/10.1109/ICESS.2008.91","url":null,"abstract":"IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.","PeriodicalId":278372,"journal":{"name":"2008 International Conference on Embedded Software and Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128831213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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