2021 IEEE 39th VLSI Test Symposium (VTS)最新文献

New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core CPU核心不可控线自动识别新技术

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441040

N. I. Deligiannis, R. Cantoro, M. Sauer, B. Becker, M. Reorda

引用次数: 3

Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks 多位盲:RSA对抗侧信道攻击的对策

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441035

Abdullah Aljuffri, C. Reinbrecht, S. Hamdioui, M. Taouil

{"title":"Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks","authors":"Abdullah Aljuffri, C. Reinbrecht, S. Hamdioui, M. Taouil","doi":"10.1109/VTS50974.2021.9441035","DOIUrl":"https://doi.org/10.1109/VTS50974.2021.9441035","url":null,"abstract":"Asymmetric algorithms such as RSA are considered secure from an algorithmic point of view, yet their implementations are typically vulnerable as they are used by attackers to comprise the secret key. Many countermeasures have been proposed to thwart these attacks. However, they are typically broken as the key can be easily compromised when attackers succeed figuring out which part of the traces belong to the square and multiply operations. In this paper, a new countermeasure is proposed against side channel attacks, referred to as multi-bit blinding. The proposed method provides a constant execution behavior regardless of the key value without additional cost (i.e., dummy/extra operations). It realizes this by considering multiple bits of the key (i.e., two in this paper) simultaneously and always perform the same operations on them independent of the two-bit value. This makes attacks much harder as the attacker cannot retrieve the key simply by identifying the operations. Instead, the attackers need to guess the correct values of the operations as well. As a case study, the security of an RSA algorithm implementation based on the proposed method is evaluated. Our experimental results show that the new method is secure against profiled and non-profiled side channel attacks with less overhead than currently published countermeasures.","PeriodicalId":278302,"journal":{"name":"2021 IEEE 39th VLSI Test Symposium (VTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120979528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs 结合体系结构仿真和软件故障注入对gpu的cnn可靠性进行快速准确评估

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441044

J. E. R. Condia, F. Santos, M. Reorda, P. Rech

引用次数: 12

Special Session - Test for AI Chips: from DFT to On-line Testing 专题会议-人工智能芯片测试:从DFT到在线测试

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441057

Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo

引用次数: 1

Special Session – Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits 特别会议-测试中的机器学习:模拟、数字、内存和射频集成电路的综述

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441051

Soham Roy, S. Millican, V. Agrawal

引用次数: 11

TSV Fault Modeling and A BIST Solution for TSV Pre-bond Test TSV预粘接故障建模及BIST解决方案

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441058

Kangkang Xu, Yang Yu, Xiyuan Peng

引用次数: 3

Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions 特别会议:硬件安全CAD -自动化是采用解决方案的关键

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441032

Sohrab Aftabjahani, R. Kastner, M. Tehranipoor, Farimah Farahmandi, J. Oberg, Anders Nordstrom, Nicole Fern, Alric Althoff

{"title":"Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions","authors":"Sohrab Aftabjahani, R. Kastner, M. Tehranipoor, Farimah Farahmandi, J. Oberg, Anders Nordstrom, Nicole Fern, Alric Althoff","doi":"10.1109/VTS50974.2021.9441032","DOIUrl":"https://doi.org/10.1109/VTS50974.2021.9441032","url":null,"abstract":"Although hardware security has received significant attention in the past decade or so, security design and validation engineers and researchers in industry, academia, and government have not still been equipped with a mature security-aware toolset to automatically and effectively analyze designs for various types of security vulnerabilities at different to detect and fix the security issues or build security in designs efficiently and easily. Despite such a demand, currently, there is not an ecosystem of security-aware Electronic Design Automation (EDA) or Computer-Aided Design (CAD) tools whereas the commercial design for security and validation tools are still in their infancy. However, there exist many research works that try to come up with security analysis engines and provide solutions to address different classes of security issues such as data leakage, access control violation, side-channel leakage, hardware Trojans and malicious changes, and vulnerabilities to physical attacks, fault-injection attacks, reverse engineering attacks, and chip counterfeiting or overproduction attacks. This paper presents the foundation established by several academic and industry researchers who have been supporting the realization of an ecosystem of security-aware CAD tools with their focus on hardware security coverage and fault-injection assessment for SoC designs, and security assurance standardization for electronic design integration.","PeriodicalId":278302,"journal":{"name":"2021 IEEE 39th VLSI Test Symposium (VTS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132271430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Compact Set of LFSR Seeds for Diagnostic Tests 用于诊断试验的LFSR种子的紧凑集

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441041

I. Pomeranz

引用次数: 1

Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities 专题会议:通过芯片背面进行物理攻击:威胁、挑战和机遇

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441006

E. Amini, Kai Bartels, C. Boit, Marius Eggert, N. Herfurth, T. Kiyan, Thilo Krachenfels, Jean-Pierre Seifert, Shahin Tajik

引用次数: 2

Enabling ECC and Repair Features in an eFuse Box for Memory Repair Applications 在内存修复应用中启用eFuse盒中的ECC和修复功能

2021 IEEE 39th VLSI Test Symposium (VTS) Pub Date : 2021-04-25 DOI: 10.1109/VTS50974.2021.9441028

S. Beerla, Miguel Costa

引用次数: 0