Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)最新文献_第4页

Advances and trends in FPGA design FPGA设计的进展和趋势

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016572

M. Hutton

引用次数: 0

A VLIW low power Java processor for embedded applications 用于嵌入式应用程序的VLIW低功耗Java处理器

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016614

A. C. S. Beck, L. Carro

引用次数: 30

RTL power estimation and optimization RTL功率估计和优化

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016575

E. Macii

{"title":"RTL power estimation and optimization","authors":"E. Macii","doi":"10.1145/1016568.1016575","DOIUrl":"https://doi.org/10.1145/1016568.1016575","url":null,"abstract":"Power consumption is a key limitation in many high-performance electronic systems today, ranging from mobile telecom to portable and desktop computers, especially when moving to nanometer technologies. Power is also a showstopper for many emerging applications like ambient intelligence and sensor networks, some of which are powered autonomously. Consequently, new design techniques and tools are needed to control and limit power consumption. This tutorial introduces innovative methodologies for successfully dealing with power estimation and optimization during the early stages of the design process. In particular, the presentation offers an insight of state-of-the-art techniques for power estimation at the RTL, describing how power consumption of components like data-path macros, glue and steering logic, memories, interconnect and clock wires can be efficiently modeled for fast and accurate power estimation. Then, the presentation shifts to power optimization, covering topics such as memory hierarchy and bus interface synthesis, advanced clock gating strategies and clock tree planning solutions. Most of the aforementioned approaches to RTL power estimation and optimization have now reached a significant level of maturity, and are thus finding their way into commercial CAD tools that are currently hitting the EDA market. Strengths and limitations of the design technology that is at the basis of such tools are discussed in detail throughout this tutorial.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124952972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Characterization of MOS transistor current mismatch MOS晶体管电流失配的表征

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016585

H. Klimach, A. Arnaud, M. C. Schneider, C. Galup-Montoro

引用次数: 11

A fully integrated physical activity sensing circuit for implantable pacemakers 一种用于植入式起搏器的完全集成的身体活动传感电路

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016612

A. Arnaud, C. Galup-Montoro

引用次数: 4

An improved synthesis method for low power hardwired FIR filters 一种改进的低功耗硬连线FIR滤波器合成方法

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016632

V. S. Rosa, E. Costa, J. Monteiro, S. Bampi

{"title":"An improved synthesis method for low power hardwired FIR filters","authors":"V. S. Rosa, E. Costa, J. Monteiro, S. Bampi","doi":"10.1145/1016568.1016632","DOIUrl":"https://doi.org/10.1145/1016568.1016632","url":null,"abstract":"This work presents a method to design parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation with reduced number of adders and logic depth in the multiplier block. The proposed method uses a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, where N is the maximum number of bits in '1' state allowed for each coefficient and common subexpression elimination (CSE) among multipliers. An algorithm for selecting the best NPT coefficient set for a given filter specification is proposed. Initially, a floating point coefficient set is generated using classical methods for FIR filters and then several sets of fixed point coefficients are generated by rounding the result of the floating point coefficients multiplied by a scale factor different for each set. The coefficient sets are then converted to NPT and a frequency response for each set is obtained. Based on the frequency response, the algorithm selects the best set. This set is then used as input for a CSE algorithm, which eliminate all common subexpressions among the multipliers and generates a hardware description of the filter in VHDL for synthesis purpose. The results show significant reduction in the number of adders and logic depth of the multiplier block with a minimal degradation in the filter transfer characteristics, showing the usefulness of the proposed method for low power design of parallel filters.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1956 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130190754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Distributed arithmetic FPGA design with online scalable size and performance 分布式算法FPGA设计，具有在线可扩展的大小和性能

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016608

Klaus Danne

引用次数: 3

Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration 动态和部分FPGA自重构的实时基于lut的网络拓扑

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016583

M. Hübner, Tobias Becker, J. Becker

引用次数: 115

Non-Manhattan maze routing 非曼哈顿迷宫路线

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016637

M. Stan, F. Hamzaoglu, David Garrett

引用次数: 10

Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications 嵌入式应用实时调度算法综合中的功率和性能调优

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI: 10.1145/1016568.1016616

L. Becker, M. A. Wehrmeister, C. Pereira

引用次数: 2