Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)最新文献

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Advances and trends in FPGA design FPGA设计的进展和趋势
M. Hutton
{"title":"Advances and trends in FPGA design","authors":"M. Hutton","doi":"10.1145/1016568.1016572","DOIUrl":"https://doi.org/10.1145/1016568.1016572","url":null,"abstract":"This talk gives an overview of emerging trends in the architecture of FPGAs. The topics covered includes new FPGA architectures and upcoming research topics, the growth in FPGAs with embedded tranceivers, the segmentation of FPGA architectures into mainstream and low-cost families, the relationships between FPGAs and structured ASICs, and applications and trends in CPLDs.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"37 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133840675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VLIW low power Java processor for embedded applications 用于嵌入式应用程序的VLIW低功耗Java处理器
A. C. S. Beck, L. Carro
{"title":"A VLIW low power Java processor for embedded applications","authors":"A. C. S. Beck, L. Carro","doi":"10.1145/1016568.1016614","DOIUrl":"https://doi.org/10.1145/1016568.1016614","url":null,"abstract":"This paper presents a pioneer VLIW architecture of a native Java processor. We show that, thanks to the specific stack architecture and to the use of the VLIW technique, one is able to obtain a meaningful reduction of power dissipation, with small area overhead, when compared to other ways of executing Java in hardware. The underlying technique is based on the reuse of memory access instructions, hence reducing power during memory or cache accesses. The architecture is validated for some complex embedded applications like IMDCT computation and other data processing benchmarks.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123458841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
RTL power estimation and optimization RTL功率估计和优化
E. Macii
{"title":"RTL power estimation and optimization","authors":"E. Macii","doi":"10.1145/1016568.1016575","DOIUrl":"https://doi.org/10.1145/1016568.1016575","url":null,"abstract":"Power consumption is a key limitation in many high-performance electronic systems today, ranging from mobile telecom to portable and desktop computers, especially when moving to nanometer technologies. Power is also a showstopper for many emerging applications like ambient intelligence and sensor networks, some of which are powered autonomously. Consequently, new design techniques and tools are needed to control and limit power consumption. This tutorial introduces innovative methodologies for successfully dealing with power estimation and optimization during the early stages of the design process. In particular, the presentation offers an insight of state-of-the-art techniques for power estimation at the RTL, describing how power consumption of components like data-path macros, glue and steering logic, memories, interconnect and clock wires can be efficiently modeled for fast and accurate power estimation. Then, the presentation shifts to power optimization, covering topics such as memory hierarchy and bus interface synthesis, advanced clock gating strategies and clock tree planning solutions. Most of the aforementioned approaches to RTL power estimation and optimization have now reached a significant level of maturity, and are thus finding their way into commercial CAD tools that are currently hitting the EDA market. Strengths and limitations of the design technology that is at the basis of such tools are discussed in detail throughout this tutorial.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124952972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Characterization of MOS transistor current mismatch MOS晶体管电流失配的表征
H. Klimach, A. Arnaud, M. C. Schneider, C. Galup-Montoro
{"title":"Characterization of MOS transistor current mismatch","authors":"H. Klimach, A. Arnaud, M. C. Schneider, C. Galup-Montoro","doi":"10.1145/1016568.1016585","DOIUrl":"https://doi.org/10.1145/1016568.1016585","url":null,"abstract":"Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123035594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A fully integrated physical activity sensing circuit for implantable pacemakers 一种用于植入式起搏器的完全集成的身体活动传感电路
A. Arnaud, C. Galup-Montoro
{"title":"A fully integrated physical activity sensing circuit for implantable pacemakers","authors":"A. Arnaud, C. Galup-Montoro","doi":"10.1145/1016568.1016612","DOIUrl":"https://doi.org/10.1145/1016568.1016612","url":null,"abstract":"This paper shows the implementation of a fully integrated G/sub m/-C 0.5-7 Hz bandpass filter-amplifier with gain G=400, for a piezoelectric accelerometer which is part of a rate adaptive pacemaker. The fabricated circuit operates up to 2 V power supply, consumes only 230 nA current, and achieves 2.1 /spl mu/V/sub rms/ input noise. Detailed circuit specifications, measurements, and a comparative analysis of the system performance are presented.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132349147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An improved synthesis method for low power hardwired FIR filters 一种改进的低功耗硬连线FIR滤波器合成方法
V. S. Rosa, E. Costa, J. Monteiro, S. Bampi
{"title":"An improved synthesis method for low power hardwired FIR filters","authors":"V. S. Rosa, E. Costa, J. Monteiro, S. Bampi","doi":"10.1145/1016568.1016632","DOIUrl":"https://doi.org/10.1145/1016568.1016632","url":null,"abstract":"This work presents a method to design parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation with reduced number of adders and logic depth in the multiplier block. The proposed method uses a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, where N is the maximum number of bits in '1' state allowed for each coefficient and common subexpression elimination (CSE) among multipliers. An algorithm for selecting the best NPT coefficient set for a given filter specification is proposed. Initially, a floating point coefficient set is generated using classical methods for FIR filters and then several sets of fixed point coefficients are generated by rounding the result of the floating point coefficients multiplied by a scale factor different for each set. The coefficient sets are then converted to NPT and a frequency response for each set is obtained. Based on the frequency response, the algorithm selects the best set. This set is then used as input for a CSE algorithm, which eliminate all common subexpressions among the multipliers and generates a hardware description of the filter in VHDL for synthesis purpose. The results show significant reduction in the number of adders and logic depth of the multiplier block with a minimal degradation in the filter transfer characteristics, showing the usefulness of the proposed method for low power design of parallel filters.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1956 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130190754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Distributed arithmetic FPGA design with online scalable size and performance 分布式算法FPGA设计,具有在线可扩展的大小和性能
Klaus Danne
{"title":"Distributed arithmetic FPGA design with online scalable size and performance","authors":"Klaus Danne","doi":"10.1145/1016568.1016608","DOIUrl":"https://doi.org/10.1145/1016568.1016608","url":null,"abstract":"The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with different performance and size. Moreover, one task variant is an extension of another. Therefore, a task can change between its variants without reconfiguring the entire task footprint. As case study, we introduce an online scalable distributed arithmetic design and review the advantages.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134039722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration 动态和部分FPGA自重构的实时基于lut的网络拓扑
M. Hübner, Tobias Becker, J. Becker
{"title":"Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration","authors":"M. Hübner, Tobias Becker, J. Becker","doi":"10.1145/1016568.1016583","DOIUrl":"https://doi.org/10.1145/1016568.1016583","url":null,"abstract":"Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. If a system uses this feature the designer has to take care, that no signal lines cross the border to other reconfigurable regions. Traditional solutions connecting modules on a dynamic and partial reconfigurable system use TBUF elements for connection and separation of the functional blocks. While automatically placing and routing the design, the routing-tool sometimes uses signal lines which cross the module border. The constraints given by the designer are ignored. To solve this problem, we use slices instead of TBUF elements which leads to a benefit by using an automatic modular design flow. This paper gives an overview of the used techniques and the complete system on a Xilinx XC2V3000 FPGA.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132118406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 115
Non-Manhattan maze routing 非曼哈顿迷宫路线
M. Stan, F. Hamzaoglu, David Garrett
{"title":"Non-Manhattan maze routing","authors":"M. Stan, F. Hamzaoglu, David Garrett","doi":"10.1145/1016568.1016637","DOIUrl":"https://doi.org/10.1145/1016568.1016637","url":null,"abstract":"The availability of multiple metal layers in modern IC processes raises the possibility of using non-Manhattan routing on some of the layers in order to reduce the average interconnect length, and thus improve performance and routability. In this paper, we present novel algorithms for both Manhattan and non-Manhattan multi-layer maze routing. The algorithms in principle can be extended to an arbitrary number of layers, but the paper focuses on four-layer routing, two in horizontal and two in vertical directions for Manhattan, and one layer each in horizontal, vertical, 45-degree and 135-degree directions for non-Manhattan routing. The non-Manhattan algorithms show an improvement of up to 12.2% in average wire length compared to Manhattan routing for two general MCNC benchmarks.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122338587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications 嵌入式应用实时调度算法综合中的功率和性能调优
L. Becker, M. A. Wehrmeister, C. Pereira
{"title":"Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications","authors":"L. Becker, M. A. Wehrmeister, C. Pereira","doi":"10.1145/1016568.1016616","DOIUrl":"https://doi.org/10.1145/1016568.1016616","url":null,"abstract":"This paper evaluates how distinct real-time task scheduling algorithms impact power consumption and timing performance of embedded systems. A design space exploration methodology is proposed in order to adjust the system's power consumption by tuning the CPU frequency according to the scheduling algorithm and to the temporal requirements of the embedded application. The goal is to find an optimized configuration, selecting the right combination of a scheduling policy with a CPU frequency, so as to consume less power without missing any deadline in the application. Experiments based on a synthetic workload that simulates realistic applications demonstrate that considerable power savings can be obtained. Moreover, the paper defines guidelines to be used by system designers in order to find a configuration that best matches the design constraints and requirements.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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