2006 Workshop on High Performance Switching and Routing最新文献

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Hierarchical interworking of draft Kompella and draft Lasserre approaches for VPLS VPLS中Kompella草案和Lasserre草案的分层互连
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709700
Chiao-Wei Hsu, F.-S. Choi, W. Lai, T. Hou, Woei-Luen Shyu
{"title":"Hierarchical interworking of draft Kompella and draft Lasserre approaches for VPLS","authors":"Chiao-Wei Hsu, F.-S. Choi, W. Lai, T. Hou, Woei-Luen Shyu","doi":"10.1109/HPSR.2006.1709700","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709700","url":null,"abstract":"VPLS is an emerging technology for provider provisioned layer-2 VPN over MPLS. Two leading IETF drafts define VPLS using different approaches; debates on standardization are going on. In this paper, we propose a hierarchical interworking architecture of the two approaches to combine their advantages in a non-overlapping, hierarchical way. An efficient LDP-based auto-discovery is also proposed to assist draft Lasserre approach within an AS. We show that the proposed architecture provides lower complexity, higher scalability, and security, and is more efficient than either one of the two drafts' approaches. We also show that the proposed LDP-based auto-discovery is more efficient than draft Kompella's BGP approach and draft Stein's LDP approach from the perspectives on the number of overhead packets, and the average response time for member discovery","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114723396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Resource virtualisation of network routers 网络路由器资源虚拟化
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709674
R. McIlroy, J. Sventek
{"title":"Resource virtualisation of network routers","authors":"R. McIlroy, J. Sventek","doi":"10.1109/HPSR.2006.1709674","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709674","url":null,"abstract":"There is now considerable interest in applications that transport time-sensitive data across the best-effort Internet. We present a novel network router architecture, which has the potential to improve the quality of service guarantees provided to such flows. This router architecture makes use of virtual machine techniques, to assign an individual virtual routelet to each network flow requiring QoS guarantees. We describe a prototype of this virtual routelet architecture, and evaluate its effectiveness. Experimental results of the performance and flow partitioning of this prototype, compared with a standard software router, suggest promise in the virtual routelet architecture","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115859173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Preventing buffer-credit accumulations in switches with small, shared output queues 在具有小的共享输出队列的交换机中防止缓冲区信用累积
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709744
N. Chrysos, M. Katevenis
{"title":"Preventing buffer-credit accumulations in switches with small, shared output queues","authors":"N. Chrysos, M. Katevenis","doi":"10.1109/HPSR.2006.1709744","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709744","url":null,"abstract":"We consider a switch with small output queues, shared among the input VOQ linecards. This has been shown to be a useful abstract model for realistic buffered switching fabrics. Cells are being scheduled by a central control unit, comprising independent, single resource schedulers, working in pipeline. This unit allocates output buffer credits to the requesting VOQs. We show how particular unbalanced transient VOQ states, produced by bursty traffic, affect credit reservations: when some input temporarily constitutes a bottleneck, too many credits may get reserved for it at once, leading to poor overall performance. We propose a threshold grant throttling method to control these credit accumulations. Then, we show how, under such grant throttling, typical round-robin credit schedulers can get synchronized, thus deteriorating performance. To avoid scheduler synchronization, we propose modified round-robin disciplines. Simulations under both smooth and bursty traffic demonstrate the effectiveness of the combined method: using only a 12-cell buffers per-output, for any switch size, TV, and independently of the number of cells in transit between the linecards and the fabric, the performance achieved is very close to that of pure output queueing. We also discuss the operation of the independent input and output schedulers inside the control unit, their relation with PIM-like schedulers, and their relation with buffered crossbar schedulers","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131635942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Scalable central-stage buffered Clos-network packet switches with QoS 具有QoS的可扩展中央级缓冲的clos网络分组交换机
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709726
Feng Wang, M. Hamdi
{"title":"Scalable central-stage buffered Clos-network packet switches with QoS","authors":"Feng Wang, M. Hamdi","doi":"10.1109/HPSR.2006.1709726","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709726","url":null,"abstract":"In our previous work, we proposed a scalable packet switch architecture based on the central-stage buffered Clos-network (CBC). We analyzed the memory requirements for the CBC to emulate an output-queued (OQ) switch and left the corresponding scheduling algorithms unexplored. In this paper, we set out to find a practical algorithm to schedule packets in order for the CBC to emulate an OQ switch supporting quality of service (QoS). We observe that the CBC surprisingly extend the well-known Birkhoff-von Neumann input-queued switches, making it able to scale to large switches with many input/output ports. In particular, as far as we know, the most efficient scheduling algorithm for a Birkhoff-von Neumann switch has a time complexity of O(N4.5), where N is the number of switch ports. We show in this paper that we can reduce it to O(N2.25) by employing a multi-stage multi-layer switch implementation","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129786988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Scalable two-stage Clos-network switch and module-first matching 可扩展的两级clos网络交换和模块优先匹配
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709725
R. Rojas-Cessa, Chuan-Bi Lin
{"title":"Scalable two-stage Clos-network switch and module-first matching","authors":"R. Rojas-Cessa, Chuan-Bi Lin","doi":"10.1109/HPSR.2006.1709725","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709725","url":null,"abstract":"Clos-network switches were proposed as a scalable architecture for the implementation of large-capacity circuit switches. In packet switching, the three-stage Clos-network architecture uses small switches as modules to assemble a switch with large number of ports or aggregated ports with high data rates. However, the configuration complexity of packet Clos-network switches is high as port matching and path routing must be performed. In the majority of the existing schemes, the configuration process performs routing after port-matching is achieved, and thus making port matching expensive in hardware and time complexity for a large number of ports. Here, we reduce the configuration complexity by performing routing first and port matching afterwards in a three-stage Clos-network switch. This approach applies the reduction concept of Clos networks to the matching process. This approach results in a feasible size of schedulers for up to Exabit-capacity switches, an independent configuration of the middle stage modules from port matches, a reduction of the matching communication overhead between different stages, and a release of the switching function to the last-stage modules in a three-stage switch. By using this novel matching scheme, we show that the number of stages of a Clos-network switch can be reduced to two, and we call this the two-stage Clos-network packet switch","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Linear complexity algorithms for maximum advance deflection routing in some networks 某些网络中最大超前偏转路由的线性复杂度算法
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709694
S. Mneimneh, F. Quessette
{"title":"Linear complexity algorithms for maximum advance deflection routing in some networks","authors":"S. Mneimneh, F. Quessette","doi":"10.1109/HPSR.2006.1709694","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709694","url":null,"abstract":"We consider routing in a network with no buffers at intermediate nodes: packets must move in a synchronized manner in every time step until they reach their destinations. If contention prevents a packet from advancing, i.e. taking an outgoing link on a shortest path from its current node to its destination, it is deflected on a different link, hence the name deflection routing. One common strategy in the design of deflection routing algorithms is maximum advance, which advances a maximum number of packets at every node in every time step. We examine two settings: non capacitated networks and capacitated networks. We present linear complexity algorithms for maximum advance deflection routing in networks with topological properties as follows: When the network is non capacitated, we require that each packet can advance on at most two links from any intermediate node in the network. When the network is capacitated, we require a special condition on the links in addition to the one mentioned above. Metropolitan and wide area networks typically satisfy those conditions","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RFC 2544 performance evaluation and internal measurements for a Linux based open router 基于Linux的开放路由器的RFC 2544性能评估和内部测量
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709673
R. Bolla, R. Bruschi
{"title":"RFC 2544 performance evaluation and internal measurements for a Linux based open router","authors":"R. Bolla, R. Bruschi","doi":"10.1109/HPSR.2006.1709673","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709673","url":null,"abstract":"Recent technological advances give a good chance to do something really effective in the field of open Internet equipments, also called open routers (ORs). Some initiatives have been activated since the last few years to investigate the OR and related issues. But despite these activities, large interesting areas still require a deeper investigation. This work tries to give a contribution by reporting the results of an in-depth activity of optimization and testing realized on a PC open router architecture based on Linux software and COTS hardware. The main target approached in this paper has been the forwarding performance evaluation of different OR Linux-based SW architectures. This analysis has been performed with both external (throughput and latencies) and internal (profiling) measurements. In particular, for what concerns the external measurements, a set of RFC2544 compliant tests has been proposed and analyzed","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129489582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Boosting the performance of PC-based software routers with FPGA-enhanced network interface cards 使用fpga增强的网络接口卡提高基于pc的软件路由器的性能
2006 Workshop on High Performance Switching and Routing Pub Date : 2006-10-16 DOI: 10.1109/HPSR.2006.1709693
A. Bianco, R. Birke, G. Botto, M. Chiaberge, J. Finochietto, G. Galante, M. Mellia, Ferrante Neri, M. Petracca
{"title":"Boosting the performance of PC-based software routers with FPGA-enhanced network interface cards","authors":"A. Bianco, R. Birke, G. Botto, M. Chiaberge, J. Finochietto, G. Galante, M. Mellia, Ferrante Neri, M. Petracca","doi":"10.1109/HPSR.2006.1709693","DOIUrl":"https://doi.org/10.1109/HPSR.2006.1709693","url":null,"abstract":"The research community is devoting increasing attention to software routers based on off-the-shelf hardware and open-source operating systems running on the personal-computer (PC) architecture. Today's high-end PCs are equipped with peripheral component interconnect (PCI) shared buses enabling them to easily fit into the multi-gigabit-per-second routing segment, for a price much lower than that of commercial routers. However, commercially-available PC network interface cards (NICs) lack programmability, and require not only packets to cross the PCI bus twice, but also to be processed in software by the operating system, strongly reducing the achievable forwarding rate. It is therefore interesting to explore the performance of customizable NICs based on field-programmable gate array (FPGA) logic devices we developed and assess how well they can overcome the limitations of today's commercially-available NICs","PeriodicalId":274390,"journal":{"name":"2006 Workshop on High Performance Switching and Routing","volume":"47 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121696324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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