发布求助
文献互助 智能选刊 最新文献

Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)最新文献

筛选
英文 中文
Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models 基于抽象状态机模型的复杂软硬件系统快速动态分析
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666241
G. D. Castillo, W. Hardt
{"title":"Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models","authors":"G. D. Castillo, W. Hardt","doi":"10.1109/HSC.1998.666241","DOIUrl":"https://doi.org/10.1109/HSC.1998.666241","url":null,"abstract":"High level design decisions as HW/SW-partitioning and instrumenting of building blocks can be supported efficiently by detailed analysis of dynamic instruction usage. In many cases the instruction usage is specific to the application domain in view. We present a very fast analysis approach based on high level system models. Complex application characteristics, e.g., the average number of not interrupted instructions can be determined. This is much more than execution of, for example, C-programs can provide.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114826472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Software timing analysis using HW/SW cosimulation and instruction set simulator 软件时序分析采用软硬件协同仿真和指令集模拟器
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666239
Jie Liu, M. Lajolo, A. Sangiovanni-Vincentelli
{"title":"Software timing analysis using HW/SW cosimulation and instruction set simulator","authors":"Jie Liu, M. Lajolo, A. Sangiovanni-Vincentelli","doi":"10.1109/HSC.1998.666239","DOIUrl":"https://doi.org/10.1109/HSC.1998.666239","url":null,"abstract":"Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculated by a software performance estimation method, which is not accurate enough for hard real-time systems and complicated designs. In this paper we present an approach to integrate a clock-cycle-accurate instruction set simulator (ISS) with a fast event-based system simulator. By using the ISS, the delay of events can be measured instead of estimated. An interprocess communication architecture and a simple protocol are designed to meet the requirement of robustness and flexibility. A cached refinement scheme is presented to improve the performance at the expense of accuracy. The scheme is especially effective for applications in which the delay of basic blocks is approximately data-independent. We also discuss the implementation issues by using the Ptolemy simulation environment and the ST20 simulator as an example.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns RECOD:在硬件/软件协同设计中优化资源和内存利用的重定时启发式算法
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666251
Karam S. Chatha, R. Vemuri
{"title":"RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns","authors":"Karam S. Chatha, R. Vemuri","doi":"10.1109/HSC.1998.666251","DOIUrl":"https://doi.org/10.1109/HSC.1998.666251","url":null,"abstract":"Hardware/software designs of embedded systems are characterized by stringent performance constraints. Pipelined implementation of a design is an effective way for maximizing the performance of a design. In this paper we present a novel retiming heuristic to obtain pipelined schedules for hardware-software codesigns. The heuristic aims at maximizing the throughput of a loop oriented resource constrained codesign while minimizing its shared memory usage. The effectiveness of the proposed technique is demonstrated by experimentation.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126100182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Schedulability analysis of heterogeneous systems for performance message sequence chart 异构系统性能消息序列图的可调度性分析
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666244
F. Slomka, J. Zant, L. Lambert
{"title":"Schedulability analysis of heterogeneous systems for performance message sequence chart","authors":"F. Slomka, J. Zant, L. Lambert","doi":"10.1109/HSC.1998.666244","DOIUrl":"https://doi.org/10.1109/HSC.1998.666244","url":null,"abstract":"Telecommunication systems are often specified in the standardized languages SDL and MSC. These languages allow only the specification of pure functional aspects. To remedy this problem we have combined the language MSC and performance aspects in Performance MSC (PMSC). From a PMSC specification a task model can be derived that includes beside computation times, periods and deadlines of tasks, also absolute start times of tasks and dependencies between task. This allows us to apply an extended schedulability analysis of asynchronous tasks on heterogeneous target architectures. We present the analysis technique and demonstrate with a small example, how the algorithm can be used for the real-time analysis of a cordless telephone.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127075831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A hardware/software prototyping environment for dynamically reconfigurable embedded systems 用于动态可重构嵌入式系统的硬件/软件原型环境
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666246
Josef Fleischmann, K. Buchenrieder, Rainer Kress
{"title":"A hardware/software prototyping environment for dynamically reconfigurable embedded systems","authors":"Josef Fleischmann, K. Buchenrieder, Rainer Kress","doi":"10.1109/HSC.1998.666246","DOIUrl":"https://doi.org/10.1109/HSC.1998.666246","url":null,"abstract":"Next generation embedded systems place new demands on an efficient methodology for their design and verification. These systems have to support interaction over a network, multiple concurrent applications and changing operating conditions. Therefore, besides existing requirements like low cost and high performance, new demands like adaptivity and reconfigurability arise. Traditional design methodologies do nor support exploration and implementation of this flavor of networked embedded systems. In this paper we present a suitable methodology and a flexible experimental environment which supports design exploration and prototyping of dynamically dynamically reconfigurable embedded systems based on Java specifications.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131772432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Combining multiple models of computation for scheduling and allocation 结合多种计算模型进行调度和分配
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666231
D. Ziegenbein, R. Ernst, K. Richter, J. Teich, L. Thiele
{"title":"Combining multiple models of computation for scheduling and allocation","authors":"D. Ziegenbein, R. Ernst, K. Richter, J. Teich, L. Thiele","doi":"10.1109/HSC.1998.666231","DOIUrl":"https://doi.org/10.1109/HSC.1998.666231","url":null,"abstract":"Many applications include a variety of functions from different domains. Therefore, they are best modeled with a combination of different modeling languages. For a sound design process and improved design space utilization, these different input models should be mapped to a common representation. In this paper, we present a common internal representation that integrates the aspects of several models of computation and is targeted to scheduling and allocation. The representation is explained using an example combining a classical process model as used in real-time operating systems (RTOS) with the synchronous data flow model (SDF).","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125189422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
A case study on modeling shared memory access effects during performance analysis of HW/SW systems 硬件/软件系统性能分析中共享内存访问效果建模的案例研究
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666248
M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, A. Sangiovanni-Vincentelli
{"title":"A case study on modeling shared memory access effects during performance analysis of HW/SW systems","authors":"M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, A. Sangiovanni-Vincentelli","doi":"10.1109/HSC.1998.666248","DOIUrl":"https://doi.org/10.1109/HSC.1998.666248","url":null,"abstract":"Behavioral simulation with timing annotations derived from performance modeling and analysis is a promising alternative for use in evaluating system-level design trade-offs. The accuracy of such approaches is determined by how well the effects of various HW and SW architectural features, like the Real Time Operating System (RTOS), shared memories and buses, HW/SW communication mechanisms, etc are modeled at this level. We present a study of the effects of shared memory buses during system-level performance analysis in the POLIS co-design environment using the example of a TCP/IP Network Interface System. We demonstrate how the effects of the memory arbiter and shared memory bus can be modeled efficiently at the behavioral level, and used to evaluate various design tradeoffs. Experimental results demonstrate that modeling these effects can significantly increase the accuracy of system-level performance estimates.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115808574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems HiPART:用于实时嵌入式系统的一种新的分层半交互式硬件/软件划分方法，具有快速调试功能
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666234
T. Hollstein, J. Becker, A. Kirschbaum, M. Glesner
{"title":"HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems","authors":"T. Hollstein, J. Becker, A. Kirschbaum, M. Glesner","doi":"10.1109/HSC.1998.666234","DOIUrl":"https://doi.org/10.1109/HSC.1998.666234","url":null,"abstract":"In this contribution we present a new system-level hardware/software partitioning approach (HiPART) which is run in the frame of an integrated hardware software design methodology for embedded system design. The benefits of the approach result from an hierarchical partitioning algorithm, consisting of three phases of constructive and iterative methods. The main advantage of the system is a freely selectable degree of user interaction and manual partitioning. A permanent observation of timing constraint violations during partitioning guarantees the applicability for real-time systems.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134263308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
An analysis-based approach to composition of distributed embedded systems 基于分析的分布式嵌入式系统组成方法
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666230
P. Chou, G. Borriello
{"title":"An analysis-based approach to composition of distributed embedded systems","authors":"P. Chou, G. Borriello","doi":"10.1109/HSC.1998.666230","DOIUrl":"https://doi.org/10.1109/HSC.1998.666230","url":null,"abstract":"The growing complexity in the functionality and system architecture of embedded systems has motivated designers to raise the level of abstraction by composing the system with a mix of reusable and system-specific components. Currently, these components assume specific programming models that make them difficult to compose or retarget. The modal process model addresses the problem of control composition by separating the synchronization semantics from state unification, and by supporting automatic synthesis of control communication onto distributed architectures. By avoiding over-specifying the behavior, the components can be made more composable and the designer can more easily choose the least expensive synchronization semantics for implementing the composition. To help designers evaluate their choice, we propose a method for analyzing the properties of the composed system, including the detection of potential deadlock and livelock situations.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131114888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
TGFF: task graphs for free TGFF:免费的任务图
Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98) Pub Date : 1998-03-01 DOI: 10.1109/HSC.1998.666245
R. Dick, D. Rhodes, W. Wolf
{"title":"TGFF: task graphs for free","authors":"R. Dick, D. Rhodes, W. Wolf","doi":"10.1109/HSC.1998.666245","DOIUrl":"https://doi.org/10.1109/HSC.1998.666245","url":null,"abstract":"We present a user-controllable, general-purpose, pseudorandom task graph generator called Task Graphs For Free (TGFF). TGFF creates problem instances for use in allocation and scheduling research. It has the ability to generate independent tasks as well as task sets which are composed of partially ordered task graphs. A complete description of a scheduling problem instance is created, including attributes for processors, communication resources, tasks, and inter-task communication. The user may parametrically control the correlations between attributes. Sharing TGFF's parameter settings allows researchers to easily reproduce the examples used by others, regardless of the platform on which TGFF is run.","PeriodicalId":269781,"journal":{"name":"Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125792277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 998
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信