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Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.最新文献

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A software test program generator for verifying system-on-chips 用于验证片上系统的软件测试程序生成器
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568818
A. Cheng, C. Lim, A. Parashkevov
{"title":"A software test program generator for verifying system-on-chips","authors":"A. Cheng, C. Lim, A. Parashkevov","doi":"10.1109/HLDVT.2005.1568818","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568818","url":null,"abstract":"Design verification is crucial for successful systems-on-chips (SoCs). However, validating and proving the correctness of SoCs is often a bottleneck in the design project. This paper presents a technique to test the SoC at the system level using software application based programs. Our software application level verification methodology (SALVEM) employs test programs composed of dynamic sequences of software code segments. The SALVEM system implements a test generator to create these software test programs automatically. Experiments were conducted applying SALVEM tests to the Altera Nios SoC. A feedback verification flow is also feasible in our SALVEM system. SALVEM test runs are analyzed to direct the test generator toward important SoC scenarios.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116178536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Sequential equivalence checking based on k-th invariants and circuit SAT solving 基于k不变量的顺序等价检验与电路SAT求解
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568812
Feng Lu, K. Cheng
{"title":"Sequential equivalence checking based on k-th invariants and circuit SAT solving","authors":"Feng Lu, K. Cheng","doi":"10.1109/HLDVT.2005.1568812","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568812","url":null,"abstract":"In this paper, we first present the concept of the k-th invariant. In contrast to the traditional invariants that hold for all cycles, k-th invariants guarantee to hold only after the k-th cycle from the initial state. We then present a bounded model checker BMChecker and an invariant prover IProver, both of which are based on circuit SAT techniques. Jointly, BMChecker and IProver are used to compute the k-th invariants, and are further integrated with a sequential SAT solver for checking sequential equivalence. Experimental results demonstrate that the sequential equivalence checking framework can efficiently verify large industrial designs.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132575360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A proof of correctness for the construction of property monitors 财产监视器构造的正确性证明
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568843
K. Morin-Allory, D. Borrione
{"title":"A proof of correctness for the construction of property monitors","authors":"K. Morin-Allory, D. Borrione","doi":"10.1109/HLDVT.2005.1568843","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568843","url":null,"abstract":"We prove the correctness of an original method for generating components that capture the occurrence of events, and monitor logical and temporal properties of hardware/software embedded systems. The properties are written in PSL, under the form of assertions in declarative form. The method is based on a library of primitive digital components for the PSL temporal operators. These building blocks are interconnected to construct complex properties, resulting in a synthesizable digital module that can be properly linked to the digital system under scrutiny. The proof reported in this paper applies to the weak version of all \"foundation language\" operators.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127993740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Establishing latch correspondence for embedded circuits of PowerPC microprocessors 建立PowerPC微处理器嵌入式电路的锁存对应关系
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568811
Himyanshu Anand, J. Bhadra, A. Sen, M. Abadir, K. G. Davis
{"title":"Establishing latch correspondence for embedded circuits of PowerPC microprocessors","authors":"Himyanshu Anand, J. Bhadra, A. Sen, M. Abadir, K. G. Davis","doi":"10.1109/HLDVT.2005.1568811","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568811","url":null,"abstract":"We present a latch mapping methodology that judiciously leverages structural and functional analyses on digital sequential circuits. We make use of functional design constraints in a way to get latch correspondence information. For scanable latches we use a technique based on scan chain analysis to obtain latch correspondences. We also provide an effective heuristic for finding latch correspondences for latches (potentially nonscanable) in complex state machines having cyclic dependencies. Our methodology not only answers latch correspondence, but also provides polarity of the correspondence. This is a major advantage over earlier latch mapping algorithms. Experimental results obtained on embedded circuits from live PowerPCreg design projects have shown that our technique fares better than a leading vendor tool in mapping latches - in both quantitative (more latches mapped) and performance (time/memory used) aspects","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122557768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VERISEC: verifying equivalence of sequential circuits using SAT VERISEC:使用SAT验证顺序电路的等效性
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568813
M. Syal, M. Hsiao
{"title":"VERISEC: verifying equivalence of sequential circuits using SAT","authors":"M. Syal, M. Hsiao","doi":"10.1109/HLDVT.2005.1568813","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568813","url":null,"abstract":"In this paper we propose a framework to verify equivalence of sequential circuits using Boolean satisfiability (SAT). We tackle a problem that is harder than the traditional sequential hardware equivalence; specifically, we address the uninvestigated problem of verifying delay replaceability as stated in V. Singhal et al. (2001) of two sequential designs. This notion of sequential equivalence does not make any assumptions either about the design-environment or about the design's steady state behavior. Thus, verifying delay replaceability is considered as hard as verifying safe replaceability according to V. Singhal et al. (2001) of sequential circuits (conjectured as EXPSPACE complete). Our SAT-based framework has the following salient features: (a) a methodology to inductively prove equivalence (delay replaceability) of sequential circuits with no assumptions about any initial state; (b) a scheme to include sequential logic implications into the framework; and (c) a low-cost scheme to identify equivalent flip-flop pairs on the fly. We used our tool to successfully verify several sequential benchmark circuits. Low execution times make our framework practical and scalable.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126310315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Formal verification of high-level conformance with symbolic simulation 对符号化仿真的高层符号化验证
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568830
R. Kaivola, A. Naik
{"title":"Formal verification of high-level conformance with symbolic simulation","authors":"R. Kaivola, A. Naik","doi":"10.1109/HLDVT.2005.1568830","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568830","url":null,"abstract":"We describe a practical methodology for large-scale full formal validation of industrial circuits. The approach targets conformance of register-transfer level circuit descriptions with abstract high-level models. It is supported by a proof tool that combines symbolic simulation with human-generated inductive invariants. The approach has emerged from extensive experiences in the validation of key parts of Intel IA-32 microprocessor designs, and it has allowed us to completely verify feedback-intensive circuits beyond the capabilities of most other tools. We discuss the methodology the context of two case studies: a register file bypass network and a cache invalidation protocol.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134148396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Advanced analysis techniques for cross-product coverage 跨产品覆盖的高级分析技术
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568842
Hezi Azatchi, L. Fournier, A. Ziv, Keren Zohar
{"title":"Advanced analysis techniques for cross-product coverage","authors":"Hezi Azatchi, L. Fournier, A. Ziv, Keren Zohar","doi":"10.1109/HLDVT.2005.1568842","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568842","url":null,"abstract":"Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequately tested. Because of their sheer size, the analysis of large coverage models can be an intimidating and time-consuming task. This paper presents two new techniques for coverage analysis. The first technique, coverage query, allows users that concentrate on a single uncovered event to find larger phenomena (e.g., hole) that contains this event. The second technique, quasi-hole analysis, automatically identifies large areas in the coverage space that are lightly covered. The proposed techniques provide additional means for extracting relevant, useful information, thereby improving the quality of the coverage analysis. A number of examples are provided showing how the proposed method improved the verification of actual designs.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134234554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A method for generation of GSTE assertion graphs 生成GSTE断言图的方法
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568831
Edward Smith
{"title":"A method for generation of GSTE assertion graphs","authors":"Edward Smith","doi":"10.1109/HLDVT.2005.1568831","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568831","url":null,"abstract":"Generalized symbolic trajectory evaluation (GSTE) is a formal verification technique developed by Intel and used on next-generation microprocessor designs. One of its current drawbacks is that each property must be supplied in the form of a state-transition diagram known as an assertion graph. Assertion graphs are difficult to construct, to read and to reason about because they describe properties at a low level. In this paper, we propose a higher-level property language for GSTE in which we can specify properties as what we call assertion programs. We describe a way of applying weakest precondition calculations to these programs to generate assertion graphs. These can then be supplied to existing GSTE tools for verification.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124236733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An optimum algorithm for compacting error traces for efficient functional debugging 一种压缩错误跟踪的优化算法，可实现高效的功能调试
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568834
Chia-Chih Yen, Jing-Yang Jou
{"title":"An optimum algorithm for compacting error traces for efficient functional debugging","authors":"Chia-Chih Yen, Jing-Yang Jou","doi":"10.1109/HLDVT.2005.1568834","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568834","url":null,"abstract":"Diagnosing counterexamples with error traces has acted as one of the most critical steps in functional verification. Unfortunately, error traces are normally very lengthy such that designers need to spend considerable effort to understand them. To alleviate designers' burden for debugging, we present a SAT-based algorithm for reducing the lengths of error traces. The algorithm performs the paradigm of binary search algorithm to halve the search space recursively. Furthermore, it applies a theorem to guarantee to gain the shortest lengths for the error traces. Experimental results demonstrate that our approach greatly surpasses previous work and indeed has the optimum solutions.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133173180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GASIM: a fast Galois field based simulator for functional model GASIM:一个快速的基于伽罗瓦字段的功能模型模拟器
Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568827
D. Pradhan, Ashutosh Kumar Singh, T. Rajaprabhu, A. Jabir
{"title":"GASIM: a fast Galois field based simulator for functional model","authors":"D. Pradhan, Ashutosh Kumar Singh, T. Rajaprabhu, A. Jabir","doi":"10.1109/HLDVT.2005.1568827","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568827","url":null,"abstract":"This paper presents a fast logic simulator based on Galois field. This is designed to act as an underlying tool for all finite field applications considering the fact that simulation plays an important role in all these applications. Three approaches for finite field representation and its evaluation are discussed. In addition an approach for normalizing the finite field based decision diagrams is also presented. The experimental results show the trade-off that can be made by using different design representations between spatial complexity and speed. Also the results show that it can be used in conventional simulation environment to achieve speedup.","PeriodicalId":269262,"journal":{"name":"Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123005802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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