Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware最新文献_第2页

Hardware-based simulation and collision detection for large particle systems 基于硬件的大粒子系统仿真与碰撞检测

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware Pub Date : 2004-08-29 DOI: 10.1145/1058129.1058147

Andreas Kolb, Lutz Latta, C. Rezk-Salama

{"title":"Hardware-based simulation and collision detection for large particle systems","authors":"Andreas Kolb, Lutz Latta, C. Rezk-Salama","doi":"10.1145/1058129.1058147","DOIUrl":"https://doi.org/10.1145/1058129.1058147","url":null,"abstract":"Particle systems have long been recognized as an essential building block for detail-rich and lively visual environments. Current implementations can handle up to 10,000 particles in real-time simulations and are mostly limited by the transfer of particle data from the main processor to the graphics hardware (GPU) for rendering.This paper introduces a full GPU implementation using fragment shaders of both the simulation and rendering of a dynamically-growing particle system. Such an implementation can render up to 1 million particles in real-time on recent hardware. The massively parallel simulation handles collision detection and reaction of particles with objects for arbitrary shape. The collision detection is based on depth maps that represent the outer shape of an object. The depth maps store distance values and normal vectors for collision reaction. Using a special texture-based indexing technique to represent normal vectors, standard 8-bit textures can be used to describe the complete depth map data. Alternately, several depth maps can be stored in one floating point texture.In addition, a GPU-based parallel sorting algorithm is introduced that can be used to perform a depth sorting of the particles for correct alpha blending.","PeriodicalId":266180,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124838944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 166

PixelView: a view-independent graphics rendering architecture PixelView:一个独立于视图的图形渲染架构

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware Pub Date : 2004-08-29 DOI: 10.1145/1058129.1058141

Jason Stewart, Eric P. Bennett, L. McMillan

引用次数: 22

Mio: fast multipass partitioning via priority-based instruction scheduling Mio:基于优先级指令调度的快速多通道分区

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware Pub Date : 2004-08-29 DOI: 10.1145/1058129.1058135

Andrew Riffel, A. Lefohn, Kiril Vidimce, Mark Leone, John D. Owens

{"title":"Mio: fast multipass partitioning via priority-based instruction scheduling","authors":"Andrew Riffel, A. Lefohn, Kiril Vidimce, Mark Leone, John D. Owens","doi":"10.1145/1058129.1058135","DOIUrl":"https://doi.org/10.1145/1058129.1058135","url":null,"abstract":"Real-time graphics hardware continues to offer improved resources for programmable vertex and fragment shaders. However, shader programmers continue to write shaders that require more resources than are available in the hardware. One way to virtualize the resources necessary to run complex shaders is to partition the shaders into multiple rendering passes. This problem, called the \"Multi-Pass Partitioning Problem\" (MPP), and a solution for the problem, Recursive Dominator Split (RDS), have been presented by Eric Chan et al. The O(n3) RDS algorithm and its heuristic-based O(n2) cousin, RDSh, are robust in that they can efficiently partition shaders for many architectures with varying resources. However, RDS's high runtime cost and inability to handle multiple outputs per pass make it less desirable for real-time use on today's latest graphics hardware. This paper redefines the MPP as a scheduling problem and uses scheduling algorithms that allow incremental resource estimation and pass computation in O(n log n) time. Our scheduling algorithm, Mio, is experimentally compared to RDS and shown to have better run-time scaling and produce comparable partitions for emerging hardware architectures.","PeriodicalId":266180,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123753118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

A hierarchical shadow volume algorithm 一种分层阴影体算法

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware Pub Date : 2004-08-29 DOI: 10.1145/1058129.1058132

Timo Aila, Tomas Akenine-Möller

{"title":"A hierarchical shadow volume algorithm","authors":"Timo Aila, Tomas Akenine-Möller","doi":"10.1145/1058129.1058132","DOIUrl":"https://doi.org/10.1145/1058129.1058132","url":null,"abstract":"The shadow volume algorithm is a popular technique for real-time shadow generation using graphics hardware. Its major disadvantage is that it is inherently fillrate-limited, as the performance is inversely proportional to the area of the projected shadow volumes. We present a new algorithm that reduces the shadow volume rasterization work significantly. With our algorithm, the amount of per-pixel processing becomes proportional to the screen-space length of the visible shadow boundary instead of the projected area. The first stage of the algorithm finds 8 x 8 pixel tiles, whose 3D bounding boxes are either completely inside or outside the shadow volume. After that, the second stage performs per-pixel computations only for the potential shadow boundary tiles. We outline a two-pass implementation, and also describe an efficient single-pass hardware architecture, in which the two stages are separated using a delay stream. The only modification required in applications is a new pair of calls for marking the beginning and end of a shadow volume. In our test scenes, the algorithm processes up to 11.5 times fewer pixels compared to current state-of-the-art methods, while reducing the external video memory bandwidth by a factor of up to 17.1.","PeriodicalId":266180,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127897629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware ACM SIGGRAPH/EUROGRAPHICS图形硬件会议论文集

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware Pub Date : 2002-09-01 DOI: 10.5555/569046

A. Lastra, Bengt-Olaf Schneider

引用次数: 17

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware ACM SIGGRAPH/EUROGRAPHICS图形硬件会议论文集

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware Pub Date : 1900-01-01 DOI: 10.5555/844174

引用次数: 4

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware ACM SIGGRAPH/EUROGRAPHICS图形硬件会议论文集

Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware Pub Date : 1900-01-01 DOI: 10.1145/1058129

引用次数: 14