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Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)最新文献

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A method to derive application-specific embedded processing cores 派生特定于应用程序的嵌入式处理内核的方法
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1145/334012.334029
Olivier Hébert, I. Kraljic, Y. Savaria
{"title":"A method to derive application-specific embedded processing cores","authors":"Olivier Hébert, I. Kraljic, Y. Savaria","doi":"10.1145/334012.334029","DOIUrl":"https://doi.org/10.1145/334012.334029","url":null,"abstract":"The concept of system-on-a-chip is becoming increasingly popular for the integration of complex systems. New types of processor cores are now available that enable the designer to customize their processors for the target applications. These soft cores are not tightly coupled with the target application, and this leads to processing cores sub-optimal for their specific applications. This paper proposes a method to derive application-specific embedded processors from soft processor cores. The derivation process involves an analysis of the resources of the processing core used by the target application. Then a series of optimizations based on the analysis results are performed on an optimizable model of the processor core. We present the tool used to perform the analysis of the resources used by an application, and results from a real-world case. Then, various optimization methods are described.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125852100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Program path analysis to bound cache-related preemption delay in preemptive real-time systems 抢占式实时系统中绑定缓存相关抢占延迟的程序路径分析
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1145/334012.334025
H. Tomiyama, N. Dutt
{"title":"Program path analysis to bound cache-related preemption delay in preemptive real-time systems","authors":"H. Tomiyama, N. Dutt","doi":"10.1145/334012.334025","DOIUrl":"https://doi.org/10.1145/334012.334025","url":null,"abstract":"Unpredictable behavior of cache memory makes it difficult to statically analyze the worst-case performance of real-time systems. This problem is exacerbated in case of preemptive multitask systems due to intertask cache interference, called Cache-Related Preemption Delay (CRPD). This paper proposes an approach to analysis of the tight upper bound on CRPD which a task might impose on lower-priority tasks. Our method determines the program execution path of the task which requires the maximum number of cache blocks using an integer linear programming technique. Experimental results show that our approach provides up to 69% tighter bounds on CRPD than a previous approach.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126015900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
Task response time optimization using cost-based operation motion 使用基于成本的操作动作的任务响应时间优化
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1109/HSC.2000.843717
B. Tabbara, A. Tabbara, A. Sangiovanni-Vincentelli
{"title":"Task response time optimization using cost-based operation motion","authors":"B. Tabbara, A. Tabbara, A. Sangiovanni-Vincentelli","doi":"10.1109/HSC.2000.843717","DOIUrl":"https://doi.org/10.1109/HSC.2000.843717","url":null,"abstract":"We present a technique for task response time improvement based on the concept of code motion from the software domain. Relaxed Operation Motion (ROM) is a simple yet powerful approach for performing safe and useful operation motion from heavily executed portions of a design task to less visited segments. We introduce here our algorithm, how it differs from other code motion approaches, and its application to the embedded systems domain. Results of our investigation indicate that cost-guided operation motion has the potential to improve task response time significantly.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Automatic test bench generation for simulation-based validation 基于仿真验证的自动测试台架生成
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1145/334012.334038
M. Lajolo, L. Lavagno, M. Rebaudengo, M. Reorda, M. Violante
{"title":"Automatic test bench generation for simulation-based validation","authors":"M. Lajolo, L. Lavagno, M. Rebaudengo, M. Reorda, M. Violante","doi":"10.1145/334012.334038","DOIUrl":"https://doi.org/10.1145/334012.334038","url":null,"abstract":"In current design practice synthesis tools play a key role, letting designers to concentrate on the specification of the system being designed by carrying out repetitive tasks such as architecture synthesis and technology mapping. However, in the new design flow, validation still remains a challenge: while new technologies based on formal verification are only marginally accepted for large designs, standard techniques based on simulation are beginning to fall behind the increased system complexity. This paper proposes an approach to simulation-based validation, in which an evolutionary algorithm computes useful input sequences to be included in the test bench. The feasibility of the proposed approach is assessed with a preliminary implementation of the proposed algorithm.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128865575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A generic tool set for application specific processor architectures 用于特定于应用程序的处理器体系结构的通用工具集
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1109/HSC.2000.843720
F. Engel, J. Nührenberg, G. Fettweis
{"title":"A generic tool set for application specific processor architectures","authors":"F. Engel, J. Nührenberg, G. Fettweis","doi":"10.1109/HSC.2000.843720","DOIUrl":"https://doi.org/10.1109/HSC.2000.843720","url":null,"abstract":"Retargetability allows an easy adoption of a simulator on different processor architectures without a time consuming redesign of all tools. This is evident for an efficient HW/SW codesign. In this paper we describe a tool set for fast and easy simulation of processor architectures based on a retargetable simulator core. This approach helps to reduce the development time for designing and validating System-on-a-chip (SoC) applications based on a processor core. The use of ANSI C avoids an expensive development of a modeling language. Our main focus in this paper is on conceptual decisions are made and on the structure of the tool set.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120963800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Energy estimation for 32-bit microprocessors 32位微处理器的能量估计
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1109/HSC.2000.843701
C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto
{"title":"Energy estimation for 32-bit microprocessors","authors":"C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto","doi":"10.1109/HSC.2000.843701","DOIUrl":"https://doi.org/10.1109/HSC.2000.843701","url":null,"abstract":"Estimation of software power consumption is becoming one of the major problems for many embedded applications. The paper presents a novel approach to compute the energy of an instruction set, through a suitable functional decomposition of the activities involved during instruction execution. One of the main advantages of this approach is the capability to predict the power figures of the overall instruction-set starting from a small subset. A formal discussion on the statistical properties of the model is included, together with its application on five commercial 32-bit microprocessors.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127822991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Software performance estimation strategies in a system-level design tool 系统级设计工具中的软件性能评估策略
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1145/334012.334028
Jwahar R. Bammi, W. Kruijtzer, L. Lavagno, Edwin A. Harcourt, M. Lazarescu
{"title":"Software performance estimation strategies in a system-level design tool","authors":"Jwahar R. Bammi, W. Kruijtzer, L. Lavagno, Edwin A. Harcourt, M. Lazarescu","doi":"10.1145/334012.334028","DOIUrl":"https://doi.org/10.1145/334012.334028","url":null,"abstract":"High-level cost and performance estimation, coupled with a fast hardware/software co-simulation framework, is a key enabler to a fast embedded system design cycle. Unfortunately, the problem of deriving such estimates without a detailed implementation available is difficult. In this paper we describe two approaches to solve software cost and performance estimation problem, and how they are used in an embedded system design environment. A source-based approach uses compilation onto a virtual instruction set, and allows one to quickly obtain estimates without the need for a compiler for the target processor. An object-based approach translates the assembler generated by the target compiler to \"assembler-level,\" functionally equivalent C. In both cases the code is annotated with timing and other execution related information (e.g., estimated memory accesses) and is used as a precise, yet fast, software simulation model. We contrast the precision and speed of these two techniques comparing them with those obtainable by a state-of-the-art cycle-based processor model.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116051385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 104
Instruction-level power estimation for embedded VLIW cores 嵌入式VLIW核的指令级功率估计
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1145/334012.334019
M. Sami, D. Sciuto, C. Silvano, V. Zaccaria
{"title":"Instruction-level power estimation for embedded VLIW cores","authors":"M. Sami, D. Sciuto, C. Silvano, V. Zaccaria","doi":"10.1145/334012.334019","DOIUrl":"https://doi.org/10.1145/334012.334019","url":null,"abstract":"In this paper, a power estimation methodology operating at the instruction-level is proposed. The methodology is tightly related to the characteristics of the system architecture, mainly in terms of one or more target processors, the memory sub-system, the system-level buses and the coprocessors. In this system-level framework, our main goal is to define a power model for CPU cores at the instruction level. First, the proposed power model deals with a general five-stage pipeline processor architecture, then, the model is extended to VLIW processors. The derivation of a VLIW instruction-level power model results to be intractable from the point of view of spatial complexity (which grows exponentially w.r.t. the number of possible operations in the ISA). In order to tackle this complexity, a new kind of simplification, based on the original concept of separability of processor functional units, is introduced. The proposed system-level methodology is the first step toward a more general framework to support the design of power-oriented applications through hardware/software co-design.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123911797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Low-power task scheduling for multiple devices 多设备低功耗任务调度
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1109/HSC.2000.843704
Yung-Hsiang Lu, L. Benini, G. Micheli
{"title":"Low-power task scheduling for multiple devices","authors":"Yung-Hsiang Lu, L. Benini, G. Micheli","doi":"10.1109/HSC.2000.843704","DOIUrl":"https://doi.org/10.1109/HSC.2000.843704","url":null,"abstract":"Power management saves power by shutting down idle devices. These devices often serve requests from concurrently running tasks. Ordering task execution can adjust the lengths of idle periods and exploit better opportunities for power management. This paper presents an on-line low-power scheduling algorithm for multiple devices. Simulations show that it can save up to 33% power and reduce 40% state-transition delays. This algorithm is robust under imperfect knowledge of future requests and timing constraints; therefore, it is applicable to interactive systems.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129278706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 106
Code compression as a variable in hardware/software co-design 代码压缩是硬件/软件协同设计中的一个变量
Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518) Pub Date : 2000-05-01 DOI: 10.1145/334012.334035
H. Lekatsas, J. Henkel, W. Wolf
{"title":"Code compression as a variable in hardware/software co-design","authors":"H. Lekatsas, J. Henkel, W. Wolf","doi":"10.1145/334012.334035","DOIUrl":"https://doi.org/10.1145/334012.334035","url":null,"abstract":"We present a new way to practice and view hardware/software co-design: rather than raising the level of abstraction m order to exploit the highest possible degree of optimization, we use code compression i.e. we practice at the bit-level. Through our novel architecture combined with our compression methodology this results in optimization of all major design goals/constraints. In particular, we present a compression methodology that deploys what we call a \"post-cache architecture\" (i.e. the detached decompression unit is located between the CPU and the instruction cache). We present a design methodology that allows the designer to control parameters like speed, power, and area through the choice of compression parameters. In addition we show that our compression methodology (using a Markov Model) is more efficient than the widely used Huffman compression scheme.","PeriodicalId":265672,"journal":{"name":"Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518)","volume":"293 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114041295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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