{"title":"A case for merging the ILP and DLP paradigms","authors":"Francisca Quintana, R. Espasa, M. Valero","doi":"10.1109/EMPDP.1998.647201","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647201","url":null,"abstract":"The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved using either paradigm on its own. We will show that the combination of the two techniques yields very high performance at a low cost and a low complexity. We will show that this architecture can reach a performance equivalent to a superscalar processor that sustained 10 instructions per cycle. We will see that the machine exploiting both types of parallelism improves upon the ILP-only machine by factors of 1.5-1.8. We also present a study on the scalability of both paradigms and show that, when we increase resources to reach a 16-issue machine, the advantage of the ILP+DLP machine over the ILP-only machine increases up to 2.0-3.45. While the peak achieved IPC for the ILP machine is 4, the ILP+DLP machine exceeds 10 instructions per cycle.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"198 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127026362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A flexible state-saving library for message-passing systems","authors":"A. Clematis, Geert Deconinck, V. Gianuzzi","doi":"10.1109/EMPDP.1998.647217","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647217","url":null,"abstract":"Message passing applications on a distributed computer require tools to integrate state saving and rollback, to support dynamic program reconfiguration, fault tolerance and others. The paper presents the results of integrating two independently developed tools that combine flexibility and portability. The User-Triggered CheckPointing (UTCP) provides checkpointing and recovery while relying on the programmer to indicate the position of the recovery line and the contents of the checkpoint. The tool PVMsnap provides an extension to PVM to obtain a consistent cut of the message passing application. The combination of both tools results in a portable and flexible solution for fault tolerance which can be adapted to the applications' needs.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129931132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting the parallel divide-and-conquer method to solve the symmetric tridiagonal eigenproblem","authors":"J. M. Badía, A. Vidal","doi":"10.1109/EMPDP.1998.647173","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647173","url":null,"abstract":"In this paper we present a new divide-and-conquer parallel algorithm to compute the eigenvalues of symmetric tridiagonal matrices. This algorithm combines the use of rank-one modifications in the division phase and the application of the Laguerre iteration in the updating phase. Our method is compared with one based on the same scheme but using rank-two modifications. A thorough experimental analysis in the Cray T3D parallel computer has been carried out. Special emphasis has been put on analysing the influence of the deflation phenomena on the computational cost of this kind of algorithm. Experimental results show that an adequate exploitation of the inherent parallelism in the divide-and-conquer scheme produces very efficient parallel algorithms. The obtained speedups clearly improve the best sequential algorithm, including the standard implementation of QR iteration in LAPACK.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121033842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. D. Florio, Geert Deconinck, M. Truyens, W. Rosseel, R. Lauwereins
{"title":"A hypermedia distributed application for monitoring and fault-injection in embedded fault-tolerant parallel programs","authors":"V. D. Florio, Geert Deconinck, M. Truyens, W. Rosseel, R. Lauwereins","doi":"10.1109/EMPDP.1998.647219","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647219","url":null,"abstract":"We describe a distributed, multimedia application which is being developed in the framework of the ESPRIT-IV Project 21012 EFTOS (Embedded Fault-Tolerant Supercomputing). The application dynamically sets up a hierarchy of HTML pages reflecting the current status of an EFTOS compliant dependable application running on a Parsytec CC system. These pages are fed to a World Wide Web browser playing the role of a hypermedia monitor. The adopted approach allows the user to concentrate on the high level aspects of his/her application so to quickly assess the quality of its current fault tolerance design. This view of the system lends itself well for being coupled with a tool to interactively inject software faults in the user application; this tool is currently under development.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114260500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using channel pipelining in reconfigurable interconnection networks","authors":"J. L. Sánchez, J. Duato, José M. García","doi":"10.1109/EMPDP.1998.647188","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647188","url":null,"abstract":"The major problem in wormhole routing networks is related with the contention due to message blocking. Reconfigurable networks are an alternative to reduce the negative effect that congestion produces on the performance of the network. Our work is focused on dynamic reconfiguration. This technique consists basically of placing the different processors in the network in those positions which, at each computational moment and according to the existing communication pattern among them, are more adequate for the development of such computation. In a reconfigurable architecture, the clock period is determined by the transmission time across the switch. To increase this frequency the channel pipelined technique is used. In this paper we present the foundations of reconfigurable network architecture. We show the general structure of the reconfigurable systems and we indicate the characteristics of the channel pipelining technique. Finally, we evaluate the performance of a reconfigurable system.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121644218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Developing non-local iterative parallel algorithms for GIS on a workstation network","authors":"A. Clematis, A. Coda, M. Spagnuolo","doi":"10.1109/EMPDP.1998.647206","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647206","url":null,"abstract":"The use of parallel computing is gaining increasing popularity in geographic information systems applications. There exists a class of spatial analysis algorithms that are based on local computation and are single step, hence leading to simple and efficient parallel code. For another class of algorithms it is not possible to make any assumption about the locality of computation, for example when extracting complex or global terrain features, and a number of iteration may be necessary to satisfy a convergence criteria, giving rise to non-local iterative algorithms. An example is the algorithm to extract drainage basins from digital terrain models. Despite the increasing difficulties there is an interest in parallelising non-local iterative algorithms. In this paper we present and compare different approaches to the parallelisation of non-local iterative algorithms on a workstation network using the Linda model of parallel programming.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128022061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Carrión, C. Izu, J. Gregorio, F. Vallejo, R. Beivide
{"title":"Ghost packets: a deadlock-free solution for k-ary n-cube networks","authors":"C. Carrión, C. Izu, J. Gregorio, F. Vallejo, R. Beivide","doi":"10.1109/EMPDP.1998.647190","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647190","url":null,"abstract":"Improving interconnection subsystems is crucial for the overall performance of a multicomputer system. Hence, a theoretical presentation of a new deadlockfree message flow model for k-ary n-cube networks is developed in this paper. The key idea of this flow control mechanism is to preserve enough free resources for each possible routing dependency cycle, so that packet progress will be guaranteed. Based on this algorithm, we have proposed a simple router structure for a 2-ary n-cube topology with dimensional order routing. Edge or shared buffering can be used, requiring a minimum capacity of one packet per channel. Virtual channels are eliminated, reducing router complexity and, consequently, decreasing network latency at lour loads. In fact, the performance evaluation for the 2-ary n-cube with different loads shows an improvement in the latency parameter of about 20% with respect to a deterministic routing with two virtual channels.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133027972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Work platforms: basic infrastructure for groupware-a conceptual framework","authors":"Burkhard Messer, K. Sandkuhl","doi":"10.1109/EMPDP.1998.647214","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647214","url":null,"abstract":"In the past, the field of CSCW has concentrated on providing support for the cooperative and coordination aspects of human work with the help of networked computer systems. The dominant issues now are the integration of different existing tools into comprehensive CSCW systems and the interoperation of heterogeneous CSCW systems. Work platforms based on services are providing new impulses for this integration: considerable contributions to integration can be made by standardizing the component parts offered as services in a globally networked system. The resulting increased reusability cuts costs. The paper presents a concept for a work platform for groupware applications based on services within a distributed system.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132849162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. R. García, C. Rodríguez, F. Almeida, Daniel González-Morales
{"title":"Prediction of parallel algorithms performance on bus-based networks using PVM","authors":"J. R. García, C. Rodríguez, F. Almeida, Daniel González-Morales","doi":"10.1109/EMPDP.1998.647180","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647180","url":null,"abstract":"We adapt the classic sequential model used to predict the performance of communications on parallel computers to a local area network using PVM. We have discovered that the linear model using the values of the parameters (latency, transfer rate) given by the \"ping-pong\" algorithm does not predict correctly the times invested in several communication patterns. This work concentrates in one of these patterns: One to All communications. We propose an alternative experiment that takes into account the overlapping between computations and communications that arises for this pattern. We illustrate the problem and its solution using a parallel matrix multiplication algorithm based on the master-slave paradigm. The detection of this phenomenon and the determination of the new values far the parameters simplify the design of parallel algorithms and can be used to predict the appropriate number of processors to achieve maximum efficiency.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"319 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123095668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploiting write semantics in implementing partially replicated causal objects","authors":"M. Raynal, M. Ahamad","doi":"10.1109/EMPDP.1998.647193","DOIUrl":"https://doi.org/10.1109/EMPDP.1998.647193","url":null,"abstract":"To support efficient access to objects that support cooperation between users, the objects need to be replicated at nodes where they are frequently accessed. Causal consistency is a consistency criterion particularly attractive for objects shared in cooperative applications. It is based on a causality relation on read and write operations issued by concurrent processes. It only requires that writes that depend on one another be perceived in their dependence order by all processes; so, two independent writes can be perceived in a distinct order by two different processes. In message-passing systems causal consistency is usually implemented by a protocol that ensures causal delivery of all messages. In this paper we develop a new protocol for causally consistent shared objects that exploits the write semantics that can be associated with update messages. This protocol allows early delivery of update messages and can discard messages carrying obsolete values. By not requiring that all update messages be delivered in causal order this protocol improves efficiency, reduces buffering requirements and compares very favorably with protocols that implement causal objects based on causal delivery of all update messages.","PeriodicalId":265140,"journal":{"name":"Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126693508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}