2018 IEEE 26th International Conference on Network Protocols (ICNP)最新文献_第4页

CADIA: Towards Decoupling the Congestion Control for Multipath TCP CADIA:多路径TCP拥塞控制解耦研究

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00024

Kang-Peng Chen, M. Palash

{"title":"CADIA: Towards Decoupling the Congestion Control for Multipath TCP","authors":"Kang-Peng Chen, M. Palash","doi":"10.1109/ICNP.2018.00024","DOIUrl":"https://doi.org/10.1109/ICNP.2018.00024","url":null,"abstract":"Correlating the congestion control (CC) of parallel subflows of multipath TCP (MPTCP) has shown the advantage of making it fair and friendly to legacy TCP. But the correlation also leads to some new drawbacks. In this paper, we first analyze major correlated MPTCP CC algorithms through the perspective of bandwidth competition. Based on the modeling, we verify, discover, and explain three shortages of correlated CC, namely 1) limit fairness semantic; 2) render new attack surfaces; and 3) interplay with network sharing policies. We further find that decoupling the CC of subflows is more promising in solving the above issues. However, directly applying legacy TCP CC to each subflow independently would lose the benefits of correlated CC. This motivates the design of an algorithm that decouples the CC of subflows as much as possible while still making MPTCP fair and friendly. To attain this goal, we translate the goals of correlated CC into an approximation principle under the decoupled semantic. We then propose a self-Constrained And Decoupled Increase Algorithm (CADIA) that achieves the principle by adaptively detecting and constraining non-best subflows. This makes CADIA share the benefits of correlated CC algorithms, while owning no direct correlation among the CC of subflows. Extensive analysis and experiments are conducted to demonstrate the effectiveness of CADIA.","PeriodicalId":264202,"journal":{"name":"2018 IEEE 26th International Conference on Network Protocols (ICNP)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127221926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

LTSM: Lightweight and Time Sliced Measurement for Link State LTSM:链路状态的轻量级和时间切片测量

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00034

Liang Gu, Ran Ju, Zhaogui Xu, Jin Li, Feng Li

引用次数: 2

Title Page i 第1页

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/icnp.2018.00001

引用次数: 0

Verification of Generated RTL from P4 Source Code 从P4源代码生成RTL的验证

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00065

R. Iša, Pavel Benácek, V. Pus

{"title":"Verification of Generated RTL from P4 Source Code","authors":"R. Iša, Pavel Benácek, V. Pus","doi":"10.1109/ICNP.2018.00065","DOIUrl":"https://doi.org/10.1109/ICNP.2018.00065","url":null,"abstract":"The P4 is a general and platform agnostic language for the description of packet processing functionality. So far it is being supported by a number of technology companies which provided a way for programming of their devices using the P4 language. One of possible platforms is a SmartNIC - a Field Programmable Gate Array (FPGA) device which connects flexibility with high performance into a compact package. FPGA circuits are typically programmed in a Hardware Description Language (HDL) like VHDL or Verilog. These languages are hard to learn for novices and the development of a network device is very time consuming. Therefore, researchers around the world are finding a way how to automate the translation process from P4 to HDL language because such approach allows easy and fast programming of FPGA SmartNICs to a big audience of network experts. There are currently available three main compilers for the translation of P4 source to HDL — SDNet P4FPGA and P4-to-VHDL. In our best knowledge, all mentioned compilers don't provide any automated test environment which can be used repeatedly for different P4 programs. In other words, the verification environment has to be written by hand for each P4 program. Our work demonstrates a possible solution for automated verification of generated Register Transfer Level (RTL) description of a packet processing device from provided P4 source code.","PeriodicalId":264202,"journal":{"name":"2018 IEEE 26th International Conference on Network Protocols (ICNP)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124376441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Demo Abstract: Themis: Cross-Domain Resource Orchestration and Virtualization in Cellular Computing Networks 摘要:主题:蜂窝计算网络中的跨域资源编排和虚拟化

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00041

Qiang Liu, T. Han

引用次数: 1

KeySight: Troubleshooting Programmable Switches via Scalable High-Coverage Behavior Tracking 是德科技:通过可扩展的高覆盖行为跟踪故障排除可编程交换机

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00045

Yu Zhou, J. Bi, Tong Yang, K. Gao, Cheng Zhang, Jiamin Cao, Yangyang Wang

{"title":"KeySight: Troubleshooting Programmable Switches via Scalable High-Coverage Behavior Tracking","authors":"Yu Zhou, J. Bi, Tong Yang, K. Gao, Cheng Zhang, Jiamin Cao, Yangyang Wang","doi":"10.1109/ICNP.2018.00045","DOIUrl":"https://doi.org/10.1109/ICNP.2018.00045","url":null,"abstract":"The rise of programmable switches and P4 brings much flexibility to networks, but this flexibility comes with increased risks of bugs. Diagnosing these bugs is essential for network operation but is non-trivial. A potential approach is to track packet behaviors through postcards, but existing tools either generate substantial postcards (limited scalability) or only track a small proportion of packet behaviors (low coverage). In this paper, we present KeySight, a platform that troubleshoots programmable switches with high scalability and high coverage. The key idea is based on the Packet Equivalence Class (PEC) abstraction that aggregates packets with identical behaviors and generates one postcard per behavior. The PEC abstraction minimizes the number of postcards while tracking all packet behaviors. We design novel algorithms to analyze PECs of P4 programs and to implement the PEC abstraction on programmable switches. We deploy KeySight on Tofino and SmartNIC, and evaluate it against 80 P4 programs and real packet traces of over 5TB. Results show that in the premise of overseeing over 99.9% packet behaviors, KeySight reduces the number of postcards by one to two orders of magnitude when comparing with NetSight.","PeriodicalId":264202,"journal":{"name":"2018 IEEE 26th International Conference on Network Protocols (ICNP)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121771174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Virtual Network Function Deployment in Tree-Structured Networks 树状结构网络中的虚拟网络功能部署

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00023

Yang Chen, Jie Wu, Bo Ji

{"title":"Virtual Network Function Deployment in Tree-Structured Networks","authors":"Yang Chen, Jie Wu, Bo Ji","doi":"10.1109/ICNP.2018.00023","DOIUrl":"https://doi.org/10.1109/ICNP.2018.00023","url":null,"abstract":"Network Function Virtualization (NFV) evolves the implementation of network functions from expensive hardwares to software middleboxes. These software middleboxes, also called Virtual Network Functions (VNFs), are executed on switch-connected servers. Efficiently deploying such VNFs is challenging, because VNFs must fully process all flows with their traffic rates before they reach their destinations while VNF locations are restricted by the constraint of vertex capacity. In addition, each network function offers heterogeneous VNF types with different configurations of processing volumes and costs. This paper focuses on minimizing the total cost of deploying VNF instances for providing a specific network function to all flows in tree-structured networks. First we prove the NP-hardness of heterogeneous VNF deployment in a tree topology and propose a dynamic programming based solution with a pseudo-polynomial time complexity. Then we narrow down to three simplified cases by focusing on homogeneous VNFs or the linear line topology. Specifically, three algorithms are introduced: an improved dynamic programming based algorithm for deploying homogeneous VNFs in a tree topology, a performance-guaranteed algorithm for deploying heterogeneous VNFs in a linear line topology, and an optimal greedy algorithm for deploying homogeneous VNFs in a linear line topology. Extensive simulations are conducted to evaluate the performance of our algorithms.","PeriodicalId":264202,"journal":{"name":"2018 IEEE 26th International Conference on Network Protocols (ICNP)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130874255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

QDAPS: Queueing Delay Aware Packet Spraying for Load Balancing in Data Center QDAPS:用于数据中心负载均衡的队列延迟感知数据包喷洒

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00017

Jiawei Huang, Wenjun Lv, Weihe Li, Jianxin Wang, T. He

引用次数: 10

Named Data Networking with Programmable Switches 具有可编程交换机的命名数据网络

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00055

Rui Miguel, S. Signorello, Fernando M. V. Ramos

{"title":"Named Data Networking with Programmable Switches","authors":"Rui Miguel, S. Signorello, Fernando M. V. Ramos","doi":"10.1109/ICNP.2018.00055","DOIUrl":"https://doi.org/10.1109/ICNP.2018.00055","url":null,"abstract":"The Internet today is mainly used for distributing content, in a fundamental departure from its original goal of enabling communication between endpoints. As a response to this change, Named Data Networking (NDN) is a new architecture rooted on the concept of naming data, in contrast to the original paradigm based on naming hosts. This radical architectural shift results in packet processing in NDN to differ substantially from IP. As a consequence, current network equipment cannot be seamlessly extended to offer NDN data-plane functions. To address this challenge, available NDN router solutions are usually software-based, and even the highly-optimised designs tailored to specific hardware platforms present limited performance, hindering adoption. In addition, these tailor-made solutions are hardly reusable in research and production networks. The emergence of programmable switching chips and of languages to program them, like P4, brings hope for the state of affairs to change. In this paper, we present the design of an NDN router written in P4. We improve over the state-of-the-art solution by extending the NDN functionality, and by addressing its scalability limitations. A preliminary evaluation of our open-source solution running on a software target demonstrates its feasibility.","PeriodicalId":264202,"journal":{"name":"2018 IEEE 26th International Conference on Network Protocols (ICNP)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127307153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Grus: Enabling Latency SLOs for GPU-Accelerated NFV Systems Grus:为gpu加速的NFV系统启用延迟SLOs

2018 IEEE 26th International Conference on Network Protocols (ICNP) Pub Date : 2018-09-01 DOI: 10.1109/ICNP.2018.00025

Zhilong Zheng, J. Bi, Haiping Wang, Chen Sun, Heng Yu, Hongxin Hu, K. Gao, Jianping Wu

{"title":"Grus: Enabling Latency SLOs for GPU-Accelerated NFV Systems","authors":"Zhilong Zheng, J. Bi, Haiping Wang, Chen Sun, Heng Yu, Hongxin Hu, K. Gao, Jianping Wu","doi":"10.1109/ICNP.2018.00025","DOIUrl":"https://doi.org/10.1109/ICNP.2018.00025","url":null,"abstract":"Graphics Processing Unit (GPU) has been recently exploited as a hardware accelerator to improve the performance of Network Function Virtualization (NFV). However, GPU-accelerated NFV systems suffer from significant latency variation when multiple network functions (NFs) are co-located in the same machine, which prevents operators from supporting latency Service Level Objectives (SLOs). Existing research efforts to address this problem can only guarantee a limited number of SLOs with very low resource utilization efficiency. In this paper, we present the Grus framework to support latency SLOs in GPU-accelerated NFV systems. Grus thoroughly analyzes the sources of latency variation and proposes three design principles: (1) dynamic batch size setting is needed to bound packet batching latency in CPU; (2) a reordering mechanism for data transfer over PCI-E is required to guarantee the stalling time; and (3) maximizing concurrency in GPU is necessary to avoid NF execution waiting time. Guided by the principles, Grus consists of two logical layers including an infrastructure layer and a scheduling layer. The infrastructure layer is equipped with an in-CPU Reorder-able Worker Pool that could adjust batching size and packet transfer order, and in-GPU Controllable Concurrent Executors to provide maximized concurrency. The scheduling layer runs a heuristic algorithm to perform accurate and fast scheduling to guarantee SLOs based on our prediction models. We have implemented a prototype of Grus. Extensive evaluations demonstrate that Grus can significantly reduce latency variation and satisfy 4.5× more SLO terms than state-of-the-art solutions.","PeriodicalId":264202,"journal":{"name":"2018 IEEE 26th International Conference on Network Protocols (ICNP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130420087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17