2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings最新文献

An FPGA based cut-through switch optimized for one-step PTP and real-time Ethernet 基于FPGA的直通交换机，针对一步PTP和实时以太网进行了优化

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644755

Holger Flatt, J. Jasperneite, Frank Schewe

{"title":"An FPGA based cut-through switch optimized for one-step PTP and real-time Ethernet","authors":"Holger Flatt, J. Jasperneite, Frank Schewe","doi":"10.1109/ISPCS.2013.6644755","DOIUrl":"https://doi.org/10.1109/ISPCS.2013.6644755","url":null,"abstract":"This paper presents an FPGA based Ethernet cut-through switch that is optimized for one-step PTP clock synchronization and fast forwarding of real-time Ethernet frames. Whereas a standard switch ASIC provides sophisticated mechanisms for switching of non-real-time frames, an attached FPGA implements cut-through switching of real-time frames and synchronization events. Moreover, timestamping of synchronization events, one-step bridge delay compensation, peer-delay responses for power profile and a servo clock are implemented in hardware. The results show that even a low-cost Xilinx Spartan 6 FPGA comprising 47,000 Look-up tables can fulfill the requirements for switching 6 Ethernet ports at 100 Mbps. The combination of cut-through forwarding and transparent one-step clock synchronization yields to bridge delays less than 3 microseconds for both real-time Ethernet data and synchronization events. Therefore, the presented switch can be flexibly integrated into time-synchronized real-time networks in order to provide improved switching functions.","PeriodicalId":260403,"journal":{"name":"2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121539792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

White Rabbit Transparent Clock 大白兔透明钟

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644756

C. Prados

引用次数: 3

Hardware assisted COTS IEEE 1588 solution for x86 Linux and its performance evaluation 基于x86 Linux的硬件辅助COTS IEEE 1588解决方案及其性能评价

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644762

B. Ferencz, T. Kovácsházy

引用次数: 14

Analysis of lock times of PTP slave under varying network load conditions using class based queuing 使用基于类的队列分析不同网络负载条件下PTP从站的锁定时间

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644757

N. Kero, Thomas Kernen, T. Muller, M. Deniaud

引用次数: 2

Multi-path Time Protocols 多路径时间协议

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644754

Alexander Shpiner, Yoram Revah, Tal Mizrahi

引用次数: 24

IEEE 1588 implementation with FLL vs. PLL IEEE 1588的虚锁相环与锁相环的实现

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644766

Zhu Wensi

引用次数: 4

High availability IEEE 1588 nodes over IEEE 802.1aq Shortest Path Bridging networks 基于IEEE 802.1aq最短路径桥接网络的高可用性IEEE 1588节点

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644760

P. Ferrari, A. Flammini, S. Rinaldi, G. Prytz

引用次数: 12

A resilient Kalman filter based servo clock 基于弹性卡尔曼滤波的伺服时钟

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644764

G. Giorgi, C. Narduzzi

{"title":"A resilient Kalman filter based servo clock","authors":"G. Giorgi, C. Narduzzi","doi":"10.1109/ISPCS.2013.6644764","DOIUrl":"https://doi.org/10.1109/ISPCS.2013.6644764","url":null,"abstract":"The accuracy level achievable with a given synchronization system is straightforwardly related to timestamp accuracy. Therefore, different methods have been proposed in the literature for reducing measurement uncertainty in synchronization systems. However, another important problem is deciding whether a received time information is trustworthy, particularly when timing messages generated by a supposedly reliable reference, point to significant discrepancies from the local clock. This paper presents a clock servo purposely designed for working with timestamps affected by sporadic outliers. The proposed algorithm is based on a Kalman filter (KF), whose correction phase has been modified so that the calculation of the a posteriori state vector estimate depends on the reliability of time offset and frequency deviation measurements, as assessed by an innovation-based outlier detector. To achieve greater robustness, two KF clock algorithms are run in parallel, a back-up servo providing usable state estimates whenever measurement information is withheld for too long times from the primary servo through being considered unreliable. The resulting composite algorithm features a much improved stability range, while retaining a very good accuracy.","PeriodicalId":260403,"journal":{"name":"2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130944785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Using Ptides and synchronized clocks to design distributed systems with deterministic system wide timing 利用Ptides和同步时钟来设计具有确定性全系统定时的分布式系统

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644761

P. Derler, J. Eidson, S. Goose, Edward A. Lee, Slobodan Matic, Michael Zimmer

{"title":"Using Ptides and synchronized clocks to design distributed systems with deterministic system wide timing","authors":"P. Derler, J. Eidson, S. Goose, Edward A. Lee, Slobodan Matic, Michael Zimmer","doi":"10.1109/ISPCS.2013.6644761","DOIUrl":"https://doi.org/10.1109/ISPCS.2013.6644761","url":null,"abstract":"This paper discusses the use of the Ptides model of computation as a coordination language for the design of deterministic, event-driven, real-time, distributed embedded systems. Specifically, the paper shows how the use of synchronized clocks in the context of Ptides enables explicit, platform independent specification of functionality and timing. From this specification, we generate code for two target platforms: Renesas and XMOS. The generated code includes a lightweight operating system which performs scheduling, I/O and network handling as well as application specific tasks. Ptides models are developed in Ptolemy, a design and simulation environment for heterogeneous systems. This framework also contains a code generation framework which is leveraged to derive Ptides implementations from the models. We illustrate our approach by designing a simple Ptides application, a small component in a printing press responsible for on-the-fly changeover between paper rolls. We demonstrate the design process and show that the generated code exhibits identical timing at the cyber-physical boundary on multiple implementation platforms.","PeriodicalId":260403,"journal":{"name":"2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings","volume":"409 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115922240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Time/phase synchronization distribution over Optical Transport Network(OTN) 光传输网络(OTN)上的时间/相位同步分配

2013 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISPCS) Proceedings Pub Date : 2013-10-24 DOI: 10.1109/ISPCS.2013.6644758

S. Siu, Hsiu-fang Hu, Wen-Hung Tseng, Shinn-Yan Lin, Yi-Liang Lai, C. Liao

引用次数: 1