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2019 IEEE 11th International Memory Workshop (IMW)最新文献

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Training Neural Networks using Memristive Devices with Nonlinear Accumulative Behavior 使用具有非线性累积行为的记忆装置训练神经网络
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-06-20 DOI: 10.1109/IMW.2019.8739624
C. Piveteau, M. Le Gallo, R. Khaddam-Aljameh, A. Sebastian
{"title":"Training Neural Networks using Memristive Devices with Nonlinear Accumulative Behavior","authors":"C. Piveteau, M. Le Gallo, R. Khaddam-Aljameh, A. Sebastian","doi":"10.1109/IMW.2019.8739624","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739624","url":null,"abstract":"Memristive devices when organized in crossbar arrays can be used to accelerate the training of deep neural networks through in-memory computing. In this paper, we propose a scheme that addresses a key challenge, namely, the non-linear accumulative behavior of memristive devices. Data entering and leaving the memristive crossbar array is pre- and post-processed to change the effective mapping of weight matrices onto the conductance matrix. The impact of the proposed scheme is studied for training neural networks using phase-change memory (PCM) devices as synaptic elements. The scheme is shown to significantly improve the network's classification accuracy, allowing us to reach the performance of an ideal linear device.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114706886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis on Heterogeneous SSD Configuration with Quadruple-Level Cell (QLC) NAND Flash Memory 四能级单元(QLC) NAND闪存异构SSD配置分析
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739689
Yoshiki Takai, Mamoru Fukuchi, Reika Kinoshita, C. Matsui, K. Takeuchi
{"title":"Analysis on Heterogeneous SSD Configuration with Quadruple-Level Cell (QLC) NAND Flash Memory","authors":"Yoshiki Takai, Mamoru Fukuchi, Reika Kinoshita, C. Matsui, K. Takeuchi","doi":"10.1109/IMW.2019.8739689","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739689","url":null,"abstract":"This paper investigates optimal heterogeneously-integrated SSD configuration [1] with various non-volatile memories including quadruple-level cell (QLC) NAND flash [2] considering SSD performance, energy consumption and SSD endurance lifetime. Based on the design methodology of heterogeneous SSD composed of storage class memory (SCM), multi-level cell (MLC) and triple-level cell (TLC) NAND flash [1], this paper newly adds QLC and single-level cell (SLC) NAND flash as memory components and re-optimizes the memory configurations for various workloads. Four types of SSD are compared; 1) SLC/QLC NAND flash, 2) SCM/QLC NAND flash, 3) SCM/TLC/QLC NAND flash and 4) SCM/TLC NAND flash. As a result, performance of SCM/QLC NAND flash is about one-fourth of that of SCM/TLC NAND flash for all workloads because QLC NAND flash has 5.7 times longer write latency than TLC NAND flash. For cold workloads or high total SSD cost assumption, SCM/TLC NAND flash is recommended. For hot workloads with low total SSD cost assumption, however, SLC/QLC NAND flash is optimal with emphasis on better SSD endurance lifetime. Finally, SCM/TLC/QLC NAND flash is the best when considering performance and energy consumption. In particular, for write-hot application, prxy_0, SCM/TLC/QLC NAND flash achieves 67% higher IOPS/cost [1] than SCM/TLC NAND flash.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114760352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Co-Design of DNN Model Optimization for Binary ReRAM Array In-Memory Processing 二进制ReRAM阵列内存处理的DNN模型优化协同设计
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739722
Yue Guan, T. Ohsawa
{"title":"Co-Design of DNN Model Optimization for Binary ReRAM Array In-Memory Processing","authors":"Yue Guan, T. Ohsawa","doi":"10.1109/IMW.2019.8739722","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739722","url":null,"abstract":"In this work, a novel design of ReRAM neuromorphic system is proposed to process deep neural network (DNN) fully in array efficiently. A binary neural network model is constructed and optimized on MNIST dataset. The obtained model is simulated to be processed with the proposed ReRAM array. Co-design between hardware and network model optimization in software is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127421050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Read Disturb Evaluations of 3D NAND Flash for Highly Read-Intensive Edge-Computing Inference Device for Artificial Intelligence Applications 用于人工智能应用的高读密集型边缘计算推理设备的3D NAND闪存读干扰评估
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739755
P. Du, H. Lue, T. Hsu, C. Hsieh, Wei-Chen Chen, Kuo-Ping Chang, Keh-Chung Wang, Chih-Yuan Lu
{"title":"Read Disturb Evaluations of 3D NAND Flash for Highly Read-Intensive Edge-Computing Inference Device for Artificial Intelligence Applications","authors":"P. Du, H. Lue, T. Hsu, C. Hsieh, Wei-Chen Chen, Kuo-Ping Chang, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/IMW.2019.8739755","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739755","url":null,"abstract":"The coming era of artificial intelligence (AI) and the combination with internet of things (IoT) will require a large number of edge computing inference devices. We consider 3D NAND Flash has great potential to provide either near-memory or in-memory computing for low-cost high-performance inference device. One of the critical technology challenge of 3D NAND Flash for inference application is the read disturb, because in this application the NAND Flash needs to sustain continuous read over the entire product life time. In this work, we have studied how to optimize read disturb performance of single-gate vertical channel (SGVC) 3D NAND and demonstrated the possibility to meet > 10T (1E13) continuous read which may exceed 10-year usage without the need of data refresh.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133511490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Novel Logic Non-Volatile Memory with Highly Reliable Performances for Autotronic Application 具有高可靠性能的新型逻辑非易失性存储器
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739725
Chun Hsiao Li, H. Chen, Hung Yi Liao, W. Chen, Wein-Town Sun, T. H. Hsu, C-Y. Lin
{"title":"Novel Logic Non-Volatile Memory with Highly Reliable Performances for Autotronic Application","authors":"Chun Hsiao Li, H. Chen, Hung Yi Liao, W. Chen, Wein-Town Sun, T. H. Hsu, C-Y. Lin","doi":"10.1109/IMW.2019.8739725","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739725","url":null,"abstract":"A novel logic non-volatile memory (NVM), which is fabricated by generic logic CMOS process without any additional thermal budget and with only two additional mask layers for well implantation, is proposed in this paper. Compared to the traditional cell structure, the proposed memory cell features 45% cell size reduction and overall memory macro has 37.5% area shrinkage. In addition, the NVM macro performs excellent programming/erase endurance capability up to 10K cycles and good data retention at 175°C. The NVM macro can fulfill the autotronic reliability requirements of the thermal stress conditions with 125°C high temperature operating life test over 1K hours.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131779022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Spin-Orbit Torque MRAM for ultrafast embedded memories: from fundamentals to large scale technology integration 用于超高速嵌入式存储器的自旋轨道扭矩MRAM:从基础到大规模技术集成
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739466
K. Garello, F. Yasin, G. Kar
{"title":"Spin-Orbit Torque MRAM for ultrafast embedded memories: from fundamentals to large scale technology integration","authors":"K. Garello, F. Yasin, G. Kar","doi":"10.1109/IMW.2019.8739466","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739466","url":null,"abstract":"Spin-orbit torque (SOT) magnetic random access memory (MRAM) is an emerging non-volatile memory that offers efficient and reliable sub-ns switching. It is considered as a promising candidate to tackle the replacement of SRAM memories in low level caches (L1-3). In this paper, we review the fundamentals of spin-orbit torque and we describe full-scale integration of perpendicular magnetized SOT-MRAM devices on 300mm wafers, using manufacturable methods and CMOS compatible processes. We demonstrate state-of-the-art properties of W-based top-pinned magnetic tunnel junction (MTJ) with perpendicularly magnetic anisotropy (PMA) that possess large endurance (>1011), and that can be switched at subnanosecond regimes (210ps) with power as low as 130pJ on 60nm devices. We conclude by opening current research focus and recent progress made by our team.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125648451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Principles and Challenges for Binary Oxide Based Ferroelectric Memory FeFET 基于二元氧化物的铁电记忆效应场效应晶体管的原理和挑战
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739651
T. Ali, P. Polakowski, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, R. Hoffmann, M. Czernohorsky, K. Kühnel, P. Steinke, L. Eng, K. Seidel
{"title":"Principles and Challenges for Binary Oxide Based Ferroelectric Memory FeFET","authors":"T. Ali, P. Polakowski, T. Büttner, T. Kämpfe, M. Rudolph, B. Pätzold, R. Hoffmann, M. Czernohorsky, K. Kühnel, P. Steinke, L. Eng, K. Seidel","doi":"10.1109/IMW.2019.8739651","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739651","url":null,"abstract":"In this paper, we give a perspective and recent overview of the emerging memory FeFET by shading the light on different aspects of the memory operation. The key fundamental questions related to material development, device scalability effects, utilization as multi-bit storage, write conditions, and memory endurance capability are overviewed based on experimental results of the MFIS based FeFET. The opportunities and challenges for the FeFET memory are discussed with emphasis on the fundamental principles and dependencies shaping its development.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132056244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Retention and Endurance of FeFET Memory Cells ffet记忆细胞的保留和持久
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739726
T. Ma, N. Gong
{"title":"Retention and Endurance of FeFET Memory Cells","authors":"T. Ma, N. Gong","doi":"10.1109/IMW.2019.8739726","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739726","url":null,"abstract":"Despite decades of R&D, the single-transistor (1-T) memory cell based on ferroelectric-gated Field-Effect-Transistor (FeFET) has failed to commercialize as of this writing, largely due to the inadequate retention time. The recent advent of the HfO2-based ferroelectrics, however, promises to change that. The fundamental reasons for this change, which hinges on the relatively large coercive fields (Ec's) of HfO2-based ferroelectrics, will be discussed. On the other hand, the large Ec's also causes endurance problems, which is a major reliability concern. This reliability concern is the other key topic covered in this paper.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117146031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Enabling STT-MRAM in High Volume Manufacturing for LLC Applications 在有限责任公司应用的大批量制造中启用STT-MRAM
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/IMW.2019.8739745
R. Whig, C. Ching, X. Wang, P. Agrawal, D. Kim, R. Wang, J. Lei, R. Zheng, L. Xue, J. Ahn, H. Tseng, S. Kumar, W. Zhou, E. Budiarto, T. Egan, S. Venkatanarayanan, N. Khasgiwale, W. Chen, C. Zhou, M. Pakala, K. Moraes, X. Tang
{"title":"Enabling STT-MRAM in High Volume Manufacturing for LLC Applications","authors":"R. Whig, C. Ching, X. Wang, P. Agrawal, D. Kim, R. Wang, J. Lei, R. Zheng, L. Xue, J. Ahn, H. Tseng, S. Kumar, W. Zhou, E. Budiarto, T. Egan, S. Venkatanarayanan, N. Khasgiwale, W. Chen, C. Zhou, M. Pakala, K. Moraes, X. Tang","doi":"10.1109/IMW.2019.8739745","DOIUrl":"https://doi.org/10.1109/IMW.2019.8739745","url":null,"abstract":"There is a growing interest in using Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM) technology for SRAM replacement, particularly for Last Level Cache (LLC) applications. Besides LLC requirements of high performance of the MRAM cell, and array patterning, MRAM remains challenging for high volume manufacturing (HVM) because of the process complexity: deposition and growth of up to 50 layers with sub-Ångstrom precision required to optimize device performance. In this paper, we demonstrate systematic process monitoring and optimization of magnetic tunnel junction (MTJ) stack, pattering unit-processes, and fabrication hardware and capabilities to address these challenges. We present our novel solution for precision process control required for HVM: On-board Metrology (OBM™), which is integrated into the Applied Materials Fndura® PVD System used for MTJ stack deposition. OBM technology, for the first time, truly enables volume production of STT-MRAM by providing commercial in-vacuum monitoring of MTJ film properties on product wafers in real-time. OBM is a novel optical technique, which demonstrates <0.2Å sensitivity and repeatability on the key MRAM layers without impacting process throughput. OBM helps to accelerate learning in R&D and provide precise process control in HVM. We also present a study of perpendicular MTJ (pMTJs) with resistance-area product (RA) of less than 3 Ohm-$mumathrm{m}^{2}$, having world-class tunneling magnetoresistance $(mathbf{TMR}) > 150{%}$ with stable RA, TMR, and magnetic properties post 400°C anneal. We present our most recent device data with patterned MTJ diameter below 40 nm and pitch, down to 88 nm, with well-behaved switching distributions for write pulses as short as 5 ns and with excellent device stability against 400°C back-end-of-line (BEOL) baking up to 3hr.","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116343445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
From Silicon CMOS Technology to Spin Qubits 从硅CMOS技术到自旋量子比特
2019 IEEE 11th International Memory Workshop (IMW) Pub Date : 2019-05-12 DOI: 10.1109/imw.2019.8739657
L. Hutin
{"title":"From Silicon CMOS Technology to Spin Qubits","authors":"L. Hutin","doi":"10.1109/imw.2019.8739657","DOIUrl":"https://doi.org/10.1109/imw.2019.8739657","url":null,"abstract":"","PeriodicalId":260146,"journal":{"name":"2019 IEEE 11th International Memory Workshop (IMW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129246602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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