2019 IEEE International Workshop on Signal Processing Systems (SiPS)最新文献_第5页

Lattice-Reduction-Aided Symbol-Wise Intra-Iterative Interference Cancellation Detector for Massive MIMO System 大规模MIMO系统的格约简辅助符号迭代内干扰消除检测器

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020430

Hsiao-Yu Yeh, Yuan-Hao Huang

{"title":"Lattice-Reduction-Aided Symbol-Wise Intra-Iterative Interference Cancellation Detector for Massive MIMO System","authors":"Hsiao-Yu Yeh, Yuan-Hao Huang","doi":"10.1109/SiPS47522.2019.9020430","DOIUrl":"https://doi.org/10.1109/SiPS47522.2019.9020430","url":null,"abstract":"Massive multiple-input multiple-output (MIMO) system plays an important role of increasing spectral efficiency in the fifth-generation (5G) cellular communication. The MIMO detection complexity increases significantly along with the number of antennas. Thus, the design of high-performance low-complexity detector for massive MIMO is a challenging design issue for the 5G system. This paper proposes a lattice-reduction-aided (LRA) symbol-wise (SW) detection technique to enhance the performance of the intra-iterative interference cancellation (IIC) detector based on Newton’s method. The proposed SW IIC detector has near minimum-mean-square-error performance with faster convergence speed and lower computational complexity than the original IIC detector. In a 64-QAM $128 times 8$ up-link MIMO system, the proposed LRA SW IIC detector reduces about 95.35% computational complexity of the original IIC detector under the same BER performance. Considering the preprocessing complexity of the LR in the time-varying channel, the proposed LRA SW IIC detector still has lower complexity when the coherent frame size is larger than 12 MIMO symbols.","PeriodicalId":256971,"journal":{"name":"2019 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128393962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication 一种用于矩阵乘法的低功耗近似收缩阵列架构的设计与评估

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020404

Haroon Waris, Chenghua Wang, Weiqiang Liu, F. Lombardi

{"title":"Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication","authors":"Haroon Waris, Chenghua Wang, Weiqiang Liu, F. Lombardi","doi":"10.1109/SiPS47522.2019.9020404","DOIUrl":"https://doi.org/10.1109/SiPS47522.2019.9020404","url":null,"abstract":"Matrix multiplication (MM) is a basic operation for many Digital Signal Processing applications. A Systolic Array (SA) is often considered as one of the most favorable architecture to achieve high performance for matrix multiplication. In this paper, the design exploration for an approximate SA is pursued; three design schemes are proposed by introducing approximation in multiple sub-modules. An approximation factor $alpha$ is introduced; it is related to the inexact columns in the SA to explore the accuracy-efficiency trade-off present in the proposed designs. In the evaluation, an 8-bit input operand matrix multiplication is considered; the Synopsys Design Compiler at 45nm technology node is used to establish hardware-related metrics. The Error Rate (ER), Normalized Mean Error Distance (NMED) and Mean Relative Error Distance (MRED) are used as figures of merit for error analysis. Results show that the proposed architecture for 8-bit matrix multiplication with an approximation factor $alpha=7$ has the lower power consumption compared to existing inexact designs found in the technical literature with comparable NMED. In addition, a power delay product vs NMED analysis shows the proposed designs have a lower PDP so applicable to low power applications. The practicality of the proposed architecture is established by computing the Discrete Cosine Transform.","PeriodicalId":256971,"journal":{"name":"2019 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129493152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

AVX-512 Based Software Decoding for 5G LDPC Codes 基于AVX-512的5G LDPC码软件解码

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020587

Yi Xu, Wen Wang, Z. Xu, Xiqi Gao

引用次数: 3

A Unified and Flexible Eigen-Solver for Rank-Deficient Matrix in MIMO Precoding/Beamforming Applications MIMO预编码/波束形成中秩缺失矩阵的统一灵活特征求解器

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020368

Su-An Chou, A. E. Rakhmania, P. Tsai

引用次数: 0

A Distributed Detection Algorithm For Uplink Massive MIMO Systems 一种用于上行海量MIMO系统的分布式检测算法

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020489

Qiufeng Liu, Hao Liu, Ying Yan, Peng Wu

引用次数: 3

An ISAR Imaging Algorithm Based on RCA for Micro-Doppler Effect Suppression 一种基于RCA的ISAR成像微多普勒抑制算法

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020383

Xinbo Xu, Xinfei Jin, Fulin Su

引用次数: 1

A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding 一种低延迟、低复杂度的CTC波束搜索解码硬件结构

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020324

Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang, L. Du

{"title":"A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding","authors":"Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang, L. Du","doi":"10.1109/SiPS47522.2019.9020324","DOIUrl":"https://doi.org/10.1109/SiPS47522.2019.9020324","url":null,"abstract":"The recurrent neural networks (RNNs) along with connectionist temporal classification (CTC) have been widely used in many sequence to sequence tasks, including automatic speech recognition (ASR), lipreading, and scene text recognition (STR). In these systems, CTC-trained RNNs usually require specific CTC-decoders after their output layers. Many existing CTC-trained RNN inference systems use FPGA to do calculations of RNNs, and decode their outputs on CPU. However, with the development of FPGA-based RNN hardware accelerators, existing CPU-based CTC-decoder can not meet the latency requirement of them. To resolve this issue, this paper proposes an efficient hardware architecture for the CTC beam search decoder based on the decoding method reported in our previous work. The experimental results show that the system latency per sample of the CTC-decoder is only 7.19us on Xilinx xc7vx1140tflg19301 FPGA platform, which is lower than state-of-the-art RNNs. We also implement the origin algorithm on the same FPGA platform. Comparison results show that the improved one reduces the system latency per sample by 63.67%, the LUTRAMs by 97.44%, the FFs by 79.55%, and the DSPs by 50%. To the best of our knowledge, this is the first work on hardware implementation for CTC beam search decoder.","PeriodicalId":256971,"journal":{"name":"2019 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128939027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

[Copyright notice] (版权)

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/sips47522.2019.9020396

引用次数: 0

A New Inversionless Berlekamp-Massey Algorithm with Efficient Architecture 一种新的高效无反转Berlekamp-Massey算法

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020488

Chao Chen, Y. Han, Zhongfeng Wang, B. Bai

引用次数: 1

FPGA Prototyping of A Millimeter-Wave Multiple Gigabit WLAN System 毫米波多千兆无线局域网系统的FPGA原型设计

2019 IEEE International Workshop on Signal Processing Systems (SiPS) Pub Date : 2019-10-01 DOI: 10.1109/SiPS47522.2019.9020634

Dongming Ren, Kang Chen, Shengheng Liu, Yongming Huang

引用次数: 1