Andrew Anderson, James Garland, Yuan Wen, B. Barabasz, Kaveena Persand, Aravind Vasudevan, David Gregg
{"title":"Hardware and software performance in deep learning","authors":"Andrew Anderson, James Garland, Yuan Wen, B. Barabasz, Kaveena Persand, Aravind Vasudevan, David Gregg","doi":"10.1049/pbpc022e_ch6","DOIUrl":"https://doi.org/10.1049/pbpc022e_ch6","url":null,"abstract":"In recent years, deep neural networks (DNNs) have emerged as the most successful technology for many difficult problems in image, video, voice and text processing. DNNs are resource hungry and require very large amounts of computation and memory, which is a particular challenge on IoT, mobile and embedded systems. In this chapter, we outline some major performance challenges of DNNs such as computation, parallelism, data locality and memory requirements. We describe research on these problems, such as the use of existing high-performance linear algebra libraries, hardware acceleration, reduced-precision storage and arithmetic and sparse data representations. Finally, we discuss recent trends in adapting compiler and domain-specific program generation techniques to create high-performance parallel DNN programs.","PeriodicalId":254920,"journal":{"name":"Many-Core Computing: Hardware and Software","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126909738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Manycore processor architectures","authors":"Prasenjit Chakraborty, B. N. Swamy, P. Panda","doi":"10.1049/pbpc022e_ch17","DOIUrl":"https://doi.org/10.1049/pbpc022e_ch17","url":null,"abstract":"Trade-offs between performance and power have dominated the processor architecture landscape in recent times and are expected to exert a considerable influence in the future. Processing technologies ceased to provide automatic speedups across generations, leading to the reliance on architectural innovation for achieving better performance. Manycore processor systems have found their way into various computing segments ranging from mobile systems to the desktop and server space. With the advent of graphics processing units (GPUs) with a large number of processing elements into the computing space, manycore systems have become the default engine for all target computing domains. We have focused in this chapter on mainly the desktop and system-on-chip (SoC) domain, but the architectural possibilities blend in a seamless way into the other domains also. We outline a high-level classification of manycore processors and go on to describe the major architectural components typically expected in modern and future processors, with a focus on the computing elements. Issues arising out of the integration of the various components are outlined. Future trends are also identified.","PeriodicalId":254920,"journal":{"name":"Many-Core Computing: Hardware and Software","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128510123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power modelling of multicore systems","authors":"M. J. Walker, G. Merrett, B. Al-Hashimi","doi":"10.1049/PBPC022E_CH13","DOIUrl":"https://doi.org/10.1049/PBPC022E_CH13","url":null,"abstract":"The chapter first gives a brief overview of how power is consumed in CPUs before exploring the various energy-saving techniques and power management considerations. A description of different power modelling approaches and applications is presented before top-down, run-time power models are described in detail, highlighting many important, but often-overlooked, considerations. Bottom-up approaches, their accuracy, and methods of improving their representativeness are then discussed and finally, hybrid approaches are proposed.","PeriodicalId":254920,"journal":{"name":"Many-Core Computing: Hardware and Software","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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